JPS582059Y2 - 半導体収納容器 - Google Patents

半導体収納容器

Info

Publication number
JPS582059Y2
JPS582059Y2 JP1977108704U JP10870477U JPS582059Y2 JP S582059 Y2 JPS582059 Y2 JP S582059Y2 JP 1977108704 U JP1977108704 U JP 1977108704U JP 10870477 U JP10870477 U JP 10870477U JP S582059 Y2 JPS582059 Y2 JP S582059Y2
Authority
JP
Japan
Prior art keywords
storage container
thin metal
rod
semiconductor element
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977108704U
Other languages
English (en)
Other versions
JPS5435169U (ja
Inventor
美子 安田
勇 北広
Original Assignee
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電器産業株式会社 filed Critical 松下電器産業株式会社
Priority to JP1977108704U priority Critical patent/JPS582059Y2/ja
Publication of JPS5435169U publication Critical patent/JPS5435169U/ja
Application granted granted Critical
Publication of JPS582059Y2 publication Critical patent/JPS582059Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 本考案は半導体収納容器に関し、半導体素子の電極と棒
状電極とを接続するに際し交差して接続する場合の金属
細線間の接触を防止し複雑な接続配線を可能にして機能
を飛躍的に向上させることを目的とする。
すなわち、半導体素子上の電極と収納容器の棒状金属電
極（ポストと称している）を金属細線により接続する際
、複雑な配線では金属細線が交錯しそれらの接触が生じ
る。
そこで本考案はポストの高さを各々変えることにより上
記欠点を防止しうる収納容器を提供するものである。
第１図に従来のインサークル型半導体収納容器の代表例
を示した。
１はシェルで半導体素子を接着固定する領域を有してお
り、２は棒状金属電極（ポスト）で、シェルを貫通して
外部に延びている。
半導体素子３を接着固定した後、金属細線４で素子３上
の電極とこれに対応するポスト２間が結線される。
第１図は半導体素子１個で素子上の電極とポストを結線
している金属細線４がクロスしてない場合を示している
が、例えば金属細線がクロスする場合ポストのシェルか
らの高さが同じであると第２図に示す如く金属細線が短
絡する。
第２図はクロス部分を部分的に示したものであるが、ボ
ス）２ａ、２ｂの高さが等しいので金属細線４ ａ 、
４ ｂが５の部分で接触する。
さらに第３図に示す如く１個の収納容器に２個の半導体
素子を収納する場合がよくある。
この場合にも第２図と同様のことが生じる。
即ち２個の半導体素子３ ａ 、３ ｂを並列接続した
第３図は、利得を稼ぐ場合、電流増幅率を大きセする場
合によく用いられる手段であるが、この場合でも６，７
で示すごとく金属細線がクロスし接触することが多い。
本考案はこのような不都合に鑑み、金属細線が多くなっ
てもそれらの接触の起らない半導体収納容器を提供する
ものである。
第４図に本考案の一実施例による収納容器を示し、さら
に第５図に第４図の収納容器を使用して結線した例を示
す。
第４図で示すごとく、ベースとなるシェル１にベース面
から高さの異なる２種類のボス） １０．１１を用いる
。
すなわち、ポストが２組の高さから構成され１０に示す
高いポストの隣りのポスト１１は１０より低くなってい
る。
このような収納容器を使用した結線した第５図に示すご
とく、ポスト１１ ａ、１１ ｂはポスト１０ａ。
１０ｂに比べて低くなっているために、半導体素子２か
らの金属細線２０．２１および２２と２３はそれぞれ充
分間隔をあけて交差させることができる。
なお、本考案は複数のポストのうち任意のポストの高さ
を変えることにより金属細線の接触を防ぐことができる
が、第４，５図のごとく１本おきに相隣り合うポストの
高さを異ならせると金属細線接続の自由度がとくに大き
くなり、接続端子の多い集積回路に特に好適である。
このように、従来から使用されている収納容器では、第
２図、第３図に示す如くポストの高さが同じであるため
クロスする点で金属細線が接触する危険性が大であった
が、本考案による構造は、金線接続時の作業条件を変更
することなく金属細線の接触をなくすことができ、半導
体集積回路の組立作業性を高めるとともに半導体装置の
信頼性向上に大きく寄与することができる。
【図面の簡単な説明】
第１図は従来のインサークル型半導体収納容器の構造図
、第２図は従来収納容器で配線がクロスされた部分の概
略図、第３図は従来の収納容器に２個の半導体素子を収
納した構造図、第４図は本考案の一実施例にかかる収納
容器の構成国、第５図は第４図の収納容器を用いて金属
配線を施した部分構造図である。 １・・・・・・ジールミ３・・・・・・半導体素子、１
０，１０ ａ 、１０ ｂ・・・・・・高いボス）、１
１，１１ ａ 、１１ ｂ・・・・・・低いポスト、２
０．２１．２２．２３・・・・・・金属細線。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基台の中央部に半４休素子が固定され、前記半導体素子
    の周囲に複数本の棒状電極が配置され、前記棒状電極の
    うち少なくても１本の所定棒状電極が隣にある他の棒状
    電極と前記基台からの高さが異なるように形成され、第
    １の金属細線の一端が前記所定棒状電極の頂部と電気的
    に接続されるとともに他端が前記半導体素子の電極に電
    気的に接続されかつ第２の金属細線の一端が前記化の棒
    状電極の頂部と電気的に接続されるとともに他端が前記
    半導体素子の他の電極に電気的に接続されることにより
    前記第１の金属細線と第２の金属細線が交差するように
    配置されてなる半導体収納容器。
JP1977108704U 1977-08-12 1977-08-12 半導体収納容器 Expired JPS582059Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977108704U JPS582059Y2 (ja) 1977-08-12 1977-08-12 半導体収納容器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977108704U JPS582059Y2 (ja) 1977-08-12 1977-08-12 半導体収納容器

Publications (2)

Publication Number Publication Date
JPS5435169U JPS5435169U (ja) 1979-03-07
JPS582059Y2 true JPS582059Y2 (ja) 1983-01-13

Family

ID=29053999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977108704U Expired JPS582059Y2 (ja) 1977-08-12 1977-08-12 半導体収納容器

Country Status (1)

Country Link
JP (1) JPS582059Y2 (ja)

Also Published As

Publication number Publication date
JPS5435169U (ja) 1979-03-07

Similar Documents

Publication Publication Date Title
US7335966B2 (en) Configurable integrated circuit capacitor array using via mask layers
JP3154579B2 (ja) 半導体素子搭載用のリードフレーム
JP3697594B2 (ja) 低インダクタンスコンデンサ
JPS6318654A (ja) 電子装置
JPS582059Y2 (ja) 半導体収納容器
JPH01205456A (ja) Ｌｓｉ用多ピンケース
JPH04199563A (ja) 半導体集積回路用パッケージ
JPS6240817U (ja)
JPH03209733A (ja) 半導体装置
JPS63250165A (ja) 半導体装置
JPH06267745A (ja) 高周波半導体集積回路装置
JPH0452996Y2 (ja)
JPS61248456A (ja) 混成集積回路装置及びそれに使用するリ−ドフレ−ム
JPS5823469A (ja) 複合パワ−トランジスタ
JPH0747872Y2 (ja) 半導体装置
JPH06260583A (ja) 半導体パッケージ
JPS6081634U (ja) セラミツク積層コンデンサ
JPH0119395Y2 (ja)
JPH02296306A (ja) インダクタ
JPS5851527A (ja) 半導体装置
JPH02866Y2 (ja)
JPH07161908A (ja) 半導体装置
JPS58189546U (ja) 半導体装置
JPH06349845A (ja) 半導体集積回路及びその製造方法
JPH0428253A (ja) 半導体装置