JPS58197865A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS58197865A JPS58197865A JP57079977A JP7997782A JPS58197865A JP S58197865 A JPS58197865 A JP S58197865A JP 57079977 A JP57079977 A JP 57079977A JP 7997782 A JP7997782 A JP 7997782A JP S58197865 A JPS58197865 A JP S58197865A
- Authority
- JP
- Japan
- Prior art keywords
- film
- psg
- resin
- nitride film
- molded body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は樹脂封止中導体装置に関するものである。[Detailed description of the invention] The present invention relates to a resin-sealed conductor device.
バイポーラＩＣ，ＭＯ８ＩＣ＊を樹脂モールドした半導
体装置においては１字導体素子の耐湿性で最も信頼度が
高いとされているプラズマ・ナイトライド膜（プラズマ
放電な利用して被覆したシリコン窒化膜であり、８１と
Ｎの比は適当に選択する。本明細書では以下８（Ｎｆ用
いる）なパッシベイシｍ／（最終保護膜）として形成す
ることが多い。しかしここで問題となるのは樹脂とプラ
ズマナイトライドとの間の接着性が比較的に小さいこと
で、その隙間に水が浸入し、ＡＪ配−が樹脂と綾するボ
ンディングパッド部分でＡＪを腐食し、半導体製品の信
頼度を低下させるおそれがあった。Plasma nitride film (a silicon nitride film coated using plasma discharge) is considered to be the most reliable moisture resistant single conductor element in semiconductor devices made of bipolar ICs and MO8ICs* molded in resin. The ratio of 81 and N is selected appropriately.In this specification, the following passivity m/(final protective film) is often formed using 8 (Nf is used).However, the problem here is that the resin and plasma nitride Since the adhesion between the AJ and the AJ is relatively low, there is a risk that water may enter the gap and corrode the AJ at the bonding pad portion where the AJ wiring runs against the resin, reducing the reliability of semiconductor products. Ta.
本発明は上記した問題を解消するためになされたもので
あり、その目的とするところは樹脂封止形半導体装置に
おける耐湿性を向上し高信頼性のある一品な提供するこ
とにある。The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a resin-sealed semiconductor device with improved moisture resistance and high reliability.
以下実施例にそって本発明の内容を詳述する。The contents of the present invention will be described in detail below with reference to Examples.
第１図はＷ脂封止形１ｃを模個的に断面図なもって示し
たものであって、１は半導体素子が形成された半導体基
板、２は半導体基板な支持するタブ（小板）、３は外部
リード、４は半導体素子の電極端子となるパッド、５は
Ａｕワイヤでパッドと外部リードの間を接続（ボ／ディ
／グ）するものであり、６は樹脂モールド体である。FIG. 1 is a schematic cross-sectional view of the W fat sealed type 1c, in which 1 is a semiconductor substrate on which a semiconductor element is formed, 2 is a tab (small plate) that supports the semiconductor substrate, 3 is an external lead, 4 is a pad serving as an electrode terminal of a semiconductor element, 5 is an Au wire for connecting (body/die/g) between the pad and the external lead, and 6 is a resin molded body.
第２図は第１＠ＩにおけるＡ部分を拡大した断面図であ
って１本発明を適用した状態を示している。FIG. 2 is an enlarged sectional view of part A in 1@I, showing a state in which the present invention is applied.
同図において、１はＳ１単結晶からなる基板、７は表ｆ
ＦＩＩＩ化膜（Ｓ ｔ Ｏｔ膜）、８は基板ＩＫコンタ
クトするＡＡ電極でその延長部はＡ Ｊ ハツト４に接
続する。９はＳ１０．膜７を絶縁物として補強するため
の第１のＰＳＧ（リンシリケートガラス）膜である。１
０は第１のＰＳＧ膜の上にバクシペイシ冒ンとして形成
したプラズマナイトライド（８ｉＮ ）膜である。本発
明においてはこのプラズマナイトライド膜１０の表面に
第２のＰＳＧ＠ＩＩｔ形成し、樹脂封止体６との間の接
着性な向上するものである。第２のＰＥＧ膜１１は例え
ばＣＶＤ（気相化学析出）決等により約４００Ｃで厚さ
０．２μｍｉｉ度に被覆したものである。樹脂モールド
体６はこの第２のＰ８Ｇｇ１．１に接してこれｔ包囲す
るものである。なお、プラズマ・ナイトライド膜の表面
な覆う膜としてはＰＳＧの代りにリンを含まないＳｉ０
ｇガラスをＣＶＤ法により付着させてもよい。In the same figure, 1 is a substrate made of S1 single crystal, 7 is a table f
The FIII film (S t Ot film) 8 is an AA electrode that contacts the substrate IK, and its extension is connected to the A J hat 4 . 9 is S10. This is a first PSG (phosphosilicate glass) film for reinforcing the film 7 as an insulator. 1
0 is a plasma nitride (8iN) film formed as a vacuum cleaner on the first PSG film. In the present invention, a second PSG@IIt is formed on the surface of this plasma nitride film 10 to improve the adhesion between it and the resin sealing body 6. The second PEG film 11 is coated with a thickness of 0.2 μm at about 400 C by, for example, CVD (vapor phase chemical deposition). The resin mold body 6 is in contact with and surrounds the second P8Gg1.1. In addition, as a film covering the surface of the plasma nitride film, Si0, which does not contain phosphorus, is used instead of PSG.
g-glass may be deposited by CVD.
以上実施例で述べた本発明によれば、最終パッシベイシ
ｍ７であるプラズマ・ナイトライド膜と＊ｇｉｔモール
ド体との間にこれらのいずれにも接着性の良いＰＥＧ又
はｃＶＤ−ｓｉｏ、ガラスの薄膜を介在させることで両
者の接着性が高まり、４１１脂モ一ルド体のバッシペイ
シ１１／膜との剥離力なく。According to the present invention described in the above embodiments, a thin film of PEG, cVD-sio, or glass with good adhesiveness is placed between the plasma nitride film that is the final passivation m7 and the *git mold body. By interposing it, the adhesion between the two is increased, and there is no peeling force between the 411 resin mold body and the BassiPaci 11/membrane.
隙間を生じないため、樹脂モールド体等を通して侵入し
た水のたまる個所がなくなり、耐湿性が向上できる。Since no gaps are created, there are no spots where water that has entered through the resin molded body etc. accumulates, and moisture resistance can be improved.
本編発明者がパッジベージ曹ンにｔｉｌｌプラズマナイ
トライド膜の、２ａｌ使用した場合（ｂ）、プラズマナ
イトライド膜上に８００Ａ厚のＰＳＧ膜を被覆した場合
及びＩＣＩ 、プラズマナイトライド膜上に２５００Ａ
厚のＰ ８０ＩＩを被覆した場合の各々について、早導
体鋏品の高温高湿試験（プレッシャフッカテスト）（温
度：１２１Ｃ，２気圧）を行なった結果を第３図に示す
。横軸に高温高湿試験時間を。In the case where the main inventor used 2al of a till plasma nitride film on Pudgebage carbon, (b), the case where a PSG film with a thickness of 800A was coated on the plasma nitride film, and the case where the ICI, 2500A on the plasma nitride film.
FIG. 3 shows the results of a high temperature and high humidity test (pressure hookah test) (temperature: 121 C, 2 atm) of fast conductor scissors for each case coated with P 80 II thick film. The horizontal axis shows the high temperature and high humidity test time.
縦軸に累積不良率、、、にとり、累積不良率が１％に達
！するまでの時間を比較すると、（副の場合約
８０時間であるのに対してｌｂ）は約１００時間、（Ｃ
）は約１４０時間となる。The cumulative defective rate is on the vertical axis, and the cumulative defective rate has reached 1%! Comparing the time it takes for LB to reach 100 hours (compared to about 80 hours for secondary),
) is approximately 140 hours.
試験を続行しても、ＰＳＧ膜を厚く被覆したものほど累
積不良率は低く抑えられており、ＰＳＧ膜の効果は融着
Ｋａｌめられた。Even if the test was continued, the thicker the PSG film was coated, the lower the cumulative failure rate was, and the effect of the PSG film was diminished.
さらに、第４図のようＫＰＳＧ膜１１でプラズマナイト
ライド膜１０を完全に被覆した構造とすることにより、
樹脂モールド体とパッジベージ。Furthermore, by creating a structure in which the plasma nitride film 10 is completely covered with the KPSG film 11 as shown in FIG.
Resin mold body and padge page.
ン膜の接着性がいっそうよくなり耐湿性なさらに向上さ
せることができる。The adhesion of the coating film becomes even better and its moisture resistance can be further improved.
本発明は樹脂封止中導体装置、特にバイポーラＩＣ，Ｍ
Ｏ８ＩＣで高信頼度を要する場合に適用して有効である
。The present invention relates to resin-sealed conductor devices, particularly bipolar ICs, M
It is effective when applied when high reliability is required in O8IC.
第１図は樹脂封止形牛導体装置の構造を示す概略縦断面
図、
第２図および第４図は本発明を第１図の半導体装置に適
用した実施例な示し、第１図のＡ部の拡大断Ｉｆｒ図で
ある。
第３図は本発明の詳細な説明するための図である。
６・・・樹脂モールド体、１０・・・プラズマナイトラ
イド膜−１１・・・ＰＳＧ膜。FIG. 1 is a schematic vertical sectional view showing the structure of a resin-sealed conductor device; FIGS. 2 and 4 show an embodiment in which the present invention is applied to the semiconductor device shown in FIG. 1; FIG. FIG. 3 is a diagram for explaining the present invention in detail. 6...Resin mold body, 10...Plasma nitride film-11...PSG film.
Claims (1)
体装置において、半導体素子表向に最終保護膜として形
成した半導体窒化膜と樹脂体との間に半導体酸化物系ガ
ラスな介在させたことな特徴とする樹脂封止形半導体装
置。 ２、上記半導体酸化物系ガラスがＰＳＧ（ＩＪ／シリケ
ートガラス）である特許請求の範囲第１項に記載の樹脂
封止形半導体装置。[Claims] 1. In a semiconductor device formed by sealing the surroundings of a semiconductor element with an IL-resin body, a semiconductor oxide film is formed between the semiconductor nitride film formed as a final protective film on the surface of the semiconductor element and the resin body. A resin-sealed semiconductor device characterized by the presence of a glass-based material. 2. The resin-sealed semiconductor device according to claim 1, wherein the semiconductor oxide glass is PSG (IJ/silicate glass).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57079977A JPS58197865A (en) | 1982-05-14 | 1982-05-14 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57079977A JPS58197865A (en) | 1982-05-14 | 1982-05-14 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58197865A true JPS58197865A (en) | 1983-11-17 |
Family
ID=13705380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57079977A Pending JPS58197865A (en) | 1982-05-14 | 1982-05-14 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58197865A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0825646A2 (en) * | 1996-08-21 | 1998-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
-
1982
- 1982-05-14 JP JP57079977A patent/JPS58197865A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0825646A2 (en) * | 1996-08-21 | 1998-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| EP0825646A3 (en) * | 1996-08-21 | 1999-10-13 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6362528B2 (en) | 1996-08-21 | 2002-03-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6500748B2 (en) | 1996-08-21 | 2002-12-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6720658B2 (en) | 1996-08-21 | 2004-04-13 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of conductive layers |
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