JPS58192348A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58192348A JPS58192348A JP7590282A JP7590282A JPS58192348A JP S58192348 A JPS58192348 A JP S58192348A JP 7590282 A JP7590282 A JP 7590282A JP 7590282 A JP7590282 A JP 7590282A JP S58192348 A JPS58192348 A JP S58192348A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- mask
- film
- channel
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特にチャンネ
ルカット領域の形成に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to the formation of a channel cut region.
バイポーラ型の半導体装置において、該装置の絶縁耐圧
は、特性上重要な要素の1つである。前記絶縁耐圧は、
埋込層領域とチャンネルカット領域との距離で決定され
、該距離が長い根絶縁耐圧が高くなる。しかしながら前
記埋込層領域とチャンネルカット領域の距離が長ければ
半導体装置の集積度が低下する事になり好ましくない。In a bipolar semiconductor device, the dielectric strength of the device is one of the important characteristics. The dielectric strength voltage is
It is determined by the distance between the buried layer region and the channel cut region, and the longer the distance, the higher the dielectric breakdown voltage. However, if the distance between the buried layer region and the channel cut region is long, the degree of integration of the semiconductor device will decrease, which is not preferable.
従来、バイポーラ源半導体装置を形成する場合、あらか
じめエピタキシ中ル層表面よpチャンネル力、ト領域に
不純物を添加し、その後に選択酸化法により厚い酸化膜
を形成すると同時に不純物を所望の深さにまで拡散し、
前記チャンネルカット領域を形成した。しかしながら、
この形成方法では、チャンネルカット領域に添加した不
純物は、横方向にも拡散し、該拡散の距離は、深さ方向
とほぼ同じである。すなわち、エピタキシャル層が2.
0μmの場合には、チャンネルカット領域の不純物は横
方向にも約2.0μm程度拡散することになる。従って
半導体装置を製造する場合、絶縁耐圧の低下を防止する
為に、チャンネルカット領域の横方向の広がりをも考慮
して、マスクの設計を行なわなければならず、素子領域
間の距1lliヲ短かくして高集積化を計る為の1つの
欠点になっていたO
本発明の目的は上記欠点を解消し、マスク上の埋込層領
域とチャンネルカット領域の距離を従来よすも短かくし
て、かつ絶縁耐圧を低下させない半導体装置の制酸方法
を提供することにある。Conventionally, when forming a bipolar source semiconductor device, impurities are added to the surface of the epitaxial layer in advance to the p-channel region and the p-channel region, and then a thick oxide film is formed by selective oxidation, and at the same time the impurities are added to the desired depth. spread to
The channel cut area was formed. however,
In this formation method, the impurity added to the channel cut region is also diffused in the lateral direction, and the distance of the diffusion is approximately the same as in the depth direction. That is, the epitaxial layer is 2.
In the case of 0 μm, the impurities in the channel cut region will also diffuse in the lateral direction by about 2.0 μm. Therefore, when manufacturing semiconductor devices, in order to prevent a drop in dielectric strength voltage, masks must be designed taking into account the lateral extent of the channel cut region, and the distance between device regions must be reduced by 1 lli. The purpose of the present invention is to eliminate the above-mentioned drawback, shorten the distance between the buried layer region on the mask and the channel cut region compared to the conventional method, and provide insulation. An object of the present invention is to provide an anti-oxidation method for a semiconductor device that does not reduce the withstand voltage.
本発明は、半導体基板の一工面上に、選択的に設けられ
た耐酸化性材料の薄膜をマスクにして半導体基板表面を
酸化、比較的厚い酸化膜を形成する工程とチャンネルカ
ット領域の前記厚い酸化膜を選択的に除去する工程と、
残存する厚い酸化膜及び前記薄膜をマスクにして、不純
物を添加する工程と、前記残存する厚い酸化膜を除去す
る工程と、前記残存する薄膜をマスクにして再び厚い酸
化膜を形成する工程を含むことを特徴としている。The present invention includes a process of oxidizing the surface of a semiconductor substrate using a selectively provided thin film of an oxidation-resistant material as a mask to form a relatively thick oxide film on one surface of the semiconductor substrate, and a process of forming a relatively thick oxide film in a channel cut region. selectively removing the oxide film;
The method includes a step of adding impurities using the remaining thick oxide film and the thin film as a mask, a step of removing the remaining thick oxide film, and a step of forming a thick oxide film again using the remaining thin film as a mask. It is characterized by
即ち、チャンネルカット領域に不純物を添加する前に選
択酸化法で厚い酸化膜を形成することによりエピタキシ
ャル層の一部が酸化膜に変換されるのでチャンネルカッ
ト領域に不純物を添加する時には、該領域におけるエピ
タキシャル層は薄くなっており従って素子間の絶縁をと
る為にそれ程深く不純物を拡散する必要はなく同時に横
方向への拡散も防ぐことができるので絶縁耐圧を低下し
ないで、埋込層領域とチャンネルカット領域の距離を短
かくする事が可能である。That is, before adding impurities to the channel cut region, a part of the epitaxial layer is converted into an oxide film by forming a thick oxide film using a selective oxidation method. The epitaxial layer is thinner, so it is not necessary to diffuse impurities as deeply to provide insulation between elements, and at the same time, it is possible to prevent lateral diffusion, so it is possible to close the buried layer region and channel without lowering the dielectric strength. It is possible to shorten the distance of the cut area.
次に本発明を実施例により説明する。Next, the present invention will be explained by examples.
第1図乃至第6図は、本発明をバイポーラ型の半導体装
置の製造に実施した場合の主な製造工程の断面図である
。1 to 6 are cross-sectional views of the main manufacturing steps when the present invention is applied to manufacturing a bipolar type semiconductor device.
まず埋込層領域13が形成されている半導体基板11の
表面にエピタキシャル層12を形成し、該エピタキシャ
ル層12上に熱酸化膜14及びシリコン窒化膜15を形
成する。該熱酸化膜及びシリコン窒化膜はそれぞれ50
0A、100OAが適当である(第1図)。
(次に素子領域のみに残るよ
うに選択的に前記シリコン窒化膜15と熱酸化膜14を
除去する(第2図)0
次に前記残存するシリコン窒化膜15をマスクにして露
出しているエピタキシャル層12を該エピタキシャル層
の約1/2の厚さだけ酸化膜16に変換する(第3図)
0
次にフォトレジスト膜をマスクにして将来チャンネルカ
ット領域となる部分の酸化膜16を除去し開孔部17を
形成する。更に前記フォトレジスト膜を除去し、残存す
る酸化膜16及びシリコン窒化膜15t−マスクにして
、前記開孔部17より不純物を添加し、チャンネルカッ
ト領域18を形成する(第4図)。First, an epitaxial layer 12 is formed on the surface of the semiconductor substrate 11 on which the buried layer region 13 is formed, and a thermal oxide film 14 and a silicon nitride film 15 are formed on the epitaxial layer 12. The thermal oxide film and silicon nitride film each have a thickness of 50
0A and 100OA are suitable (Fig. 1).
(Next, the silicon nitride film 15 and the thermal oxide film 14 are selectively removed so that they remain only in the element region (FIG. 2). Next, the remaining silicon nitride film 15 is used as a mask to remove the exposed epitaxial film. Converting layer 12 to an oxide film 16 by approximately 1/2 the thickness of the epitaxial layer (FIG. 3).
0 Next, using the photoresist film as a mask, the oxide film 16 in a portion that will become a channel cut region in the future is removed to form an opening 17. Further, the photoresist film is removed, and using the remaining oxide film 16 and silicon nitride film 15t as a mask, impurities are added through the opening 17 to form a channel cut region 18 (FIG. 4).
次に残存する前記酸化膜16をバ、ファード弗酸液を用
いて全て除去する(第5図)0次に再び残存するシリコ
ン窒化膜15をマスクにして再び露出しているエピタキ
シャル層12を全て熱酸化膜19に変換する。この時、
前記チャンネルカット領域18は、半導体基板11内部
にまで拡散され完全に素子領域間を分離する(第6図)
0
次に残存するシリコン窒化膜15を除去し、従来法によ
り素子領域内部にトランジスタを形成し、更に金属配線
をして装置の形成を完了する。Next, the remaining oxide film 16 is completely removed using a Fard hydrofluoric acid solution (FIG. 5). Next, using the remaining silicon nitride film 15 as a mask, all of the exposed epitaxial layer 12 is removed again. It is converted into a thermal oxide film 19. At this time,
The channel cut region 18 is diffused into the interior of the semiconductor substrate 11 and completely isolates the device regions (FIG. 6).
0 Next, the remaining silicon nitride film 15 is removed, a transistor is formed inside the element region by a conventional method, and metal wiring is further formed to complete the formation of the device.
上記実施例で説明したように、本発明によればチャンネ
ルカット領域18に不純物を添加する前に、エピタキシ
ャル層12の約1/2の厚さを酸化膜16に変換するこ
とにより将来チャンネルカット領域を形成するエピタキ
シャル層12は従来の約1/2の厚さになっている為に
、チャンネルカット領域内に添加され九不純物が完全に
素子領域間を分離するまでに拡散される距離は従来より
も約1/2程少ない。従って横方向の拡散広がりも従来
よりも少なくてすむ。As explained in the above embodiments, according to the present invention, before adding impurities to the channel cut region 18, approximately 1/2 of the thickness of the epitaxial layer 12 is converted into an oxide film 16 to form a future channel cut region. Since the epitaxial layer 12 that forms the layer is approximately 1/2 the thickness of the conventional one, the distance over which the impurity doped into the channel cut region is diffused to completely separate the device regions is longer than that of the conventional one. is also about 1/2 less. Therefore, the diffusion spread in the lateral direction is also smaller than in the conventional case.
これにより半導体装置の特性に何ら重要な影響を及ぼす
ことなく、埋込層領域とチャンネル力。This reduces the buried layer area and channel forces without any significant effect on the characteristics of the semiconductor device.
ト領域の間を微細にかつ、絶縁耐圧を低下させることな
く形成することが可能である。It is possible to form a fine gap between the contact regions without reducing the dielectric strength.
以上、本発明をバイポーラ源の半導体装置に実施し九場
合を説明したが、ダイオード等を含む集積回路装置にも
適用できる。Although nine cases have been described above in which the present invention is applied to a bipolar source semiconductor device, it can also be applied to an integrated circuit device including a diode or the like.
第1図乃至第6図は本発明の半導体装置の製造方法の一
実施例の主な製造工程における断面図である。
同、図において、11・・・・・・半導体基板 12・
・・・・・エピタキシャル層、13・・・・・・埋込層
領域、14゜16.19・・・・・・酸化膜、15・・
・・・・シリコン窒化膜、17・・・・・・開孔部、1
8・・・・・・チャンネルカット領域。
篤 5 口 8
/3
X 61.¥]1 to 6 are cross-sectional views showing main manufacturing steps of an embodiment of the method for manufacturing a semiconductor device of the present invention. In the same figure, 11...semiconductor substrate 12.
...Epitaxial layer, 13...Buried layer region, 14°16.19...Oxide film, 15...
...Silicon nitride film, 17...Opening part, 1
8...Channel cut area. Atsushi 5 Mouth 8 /3 X 61. ¥]
Claims (1)
耐献化性材料の薄gをマスクにし−C′P導体基板表面
t−絃化し比較t?シ厚い酸化膜を形成する工程と、チ
ャンネル力、ト領域の−11記厚い酸化膜を選択的に除
去する工程と、残存する厚い酸化膜及び前記薄膜をマス
クにして、不純物を前記半導体基板のチャンネルカット
領域に添加する工程と、前記残存する厚い酸化膜を除去
する工程と、前記残存する薄膜をマスクにして再び厚い
酸化膜を形成する工程を含むことを特徴とする牛4体装
置の製造方法。The surface of the C'P conductor substrate (t) is compared by using a thin layer (g) of at least a corrosion-resistant material selectively provided on one surface of the semiconductor substrate as a mask. a step of forming a thick oxide film; a step of selectively removing the -11th thick oxide film in the channel region; and a step of removing impurities from the semiconductor substrate using the remaining thick oxide film and the thin film as a mask. Manufacture of a four-body cow device comprising the steps of: adding to the channel cut region; removing the remaining thick oxide film; and forming a thick oxide film again using the remaining thin film as a mask. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7590282A JPS58192348A (en) | 1982-05-06 | 1982-05-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7590282A JPS58192348A (en) | 1982-05-06 | 1982-05-06 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58192348A true JPS58192348A (en) | 1983-11-09 |
JPS6238857B2 JPS6238857B2 (en) | 1987-08-20 |
Family
ID=13589726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7590282A Granted JPS58192348A (en) | 1982-05-06 | 1982-05-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58192348A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5004701A (en) * | 1988-01-29 | 1991-04-02 | Nec Corporation | Method of forming isolation region in integrated circuit semiconductor device |
-
1982
- 1982-05-06 JP JP7590282A patent/JPS58192348A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5004701A (en) * | 1988-01-29 | 1991-04-02 | Nec Corporation | Method of forming isolation region in integrated circuit semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6238857B2 (en) | 1987-08-20 |
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