JP3325432B2 - MOS type semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench gate type vertical type.
MOS FET (Metal Oxide Semiconductor FieldEffect Tran
sistor), in particular, its wiring structure.

[0002]

2. Description of the Related Art In a highly integrated MOS FET structure, a plurality of vertical MOS FETs (see FIG. 3) in which the trench gates are covered with an insulating film 35 are formed, and a gate electrode that comes into contact with each trench gate at a time. Is formed. However, since the trench gate is made of the PolySi film 36, the above structure has a problem that the resistance is increased. Therefore, in practical use, a type in which a gate electrode made of an Al film is formed directly on the gate of each MOSFET and the wiring has a low resistance has been mainstream.

FIGS. 2A to 2H are cross-sectional views showing the steps of manufacturing a conventional trench gate type vertical MOS FET in which the gate wiring has a reduced resistance. (1) As shown in FIG. 2A, after a P-type base region 22, a P ⁺ region 23, and an N ⁺ source region 24 are formed in an N-type epitaxial layer 21 in which an N ⁺ drain layer 20 is epitaxially grown by ion implantation. Then, a Si oxide film 25A is formed on the surface. FIG.
As shown in (b), the Si oxide film 25A is patterned, and using this as a mask, the portion from the N ⁺ source region 24 to the upper portion of the N-type epitaxial layer 21 is removed by RIE to form a trench having a width of about 1 μm. Is removed.

(2) As shown in FIG. 2 (c), an Si oxide film 25B of about 20 to 100 nm is formed on the side surfaces of the trench and the surface of the substrate by thermal oxidation, and then, as shown in FIG. Until the trench is filled, an impurity-doped Poly Si film 26 is deposited.

(3) As shown in FIG. 2 (e), a poly-Si film 26 deposited on the surface of the Si oxide film 25B is patterned to form a T-shaped gate having an upper portion in contact with the gate electrode longer than the trench width. After the formation, an Si oxide film 25 of several μm is formed. Then, the source contact hole 28a and the gate contact hole 29a are opened using the patterned resist as a mask, and the resist is removed.

(4) As shown in FIG. 2 (f), an Al film is formed on the surface and a predetermined patterning is performed to form a source electrode 28 and a gate electrode 29, thereby reducing the resistance of the conventional gate electrode wiring. The trench type MOS FET is completed.

[0007]

The conventional trench-type MOS FET in which the gate electrode wiring has a low resistance has a narrow trench width of about 1 μm. Therefore, it is necessary to take account of mask misalignment when forming a gate contact hole. The contact between the gate electrode and the gate is surely formed by forming the upper part of the gate in contact with the gate electrode longer than the trench width and forming the gate from an I-shape to a T-shape.

For this reason, the area occupying the substrate is increased by the length equal to or longer than the trench width above the trench gate, and there is a problem that the degree of high integration of the device is reduced. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problems and achieve high integration of devices while maintaining the electrical characteristics of a trench type vertical MOS FET.

[0009]

In order to achieve the above object, in a method of manufacturing a MOS type semiconductor device according to the present invention, a first conductive type drain region and a second conductive type formed on the drain region are provided. Forming a first insulating film on a semiconductor substrate having a die-shaped channel forming region and a source region formed at predetermined intervals on the channel forming region; and forming the first insulating film and the source region. Forming a trench having a depth from the surface of the first insulating film to the upper part of the drain region and removing the upper part of the drain region by penetrating the source region. Forming a second insulating film on the side surface of the trench, and forming a first conductive layer on the second insulating film so as to cover the surface of the first insulating film and fill the inside of the trench. The first Forming a conductive layer, removing the first conductive layer on the first insulating film, leaving a portion of the first conductive layer in the trench to form a trench gate, After removing the layer, a predetermined portion of the first insulating film is selectively removed to expose a predetermined portion of the source region,
Forming a source contact hole, and forming a source contact hole, forming a second conductive layer, and patterning the second conductive layer to form a source electrode and a gate electrode. It is characterized by having.

A step of removing the first conductive layer;
And a step of selectively removing an upper surface of the first insulating film and setting an upper end of the first conductive film above a main surface of the first insulating film between the step of forming the source contact hole. It is characterized by the following.

[0011]

In the manufacturing process, after forming an insulating film for separating a gate and a source, a trench gate is formed. At this point, since the surface of the trench gate is exposed, the gate electrode can be formed by patterning after forming an Al film on this surface.

Therefore, there is no need to perform a step of opening a gate contact hole for making an electrical connection with a trench gate. Need not be longer than the trench width. Therefore, higher integration can be performed than before.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIGS. 1A to 1G are schematic cross-sectional views showing manufacturing steps of a semiconductor device according to a first embodiment of the present invention.

(1) As shown in FIG. 1A, a P-type base region 12, a P ⁺ region 13, and an N ⁺ source region 14 are ion-implanted into an N-type epitaxial layer 11 on which an N ⁺ drain layer 10 is epitaxially grown. After the formation, an Si oxide film 25A of about 1 μm is sequentially formed on the surface, and a Si oxide film pattern is formed by predetermined patterning of the surface. Using this Si oxide film pattern as a mask, N ⁺ is removed from the surface of the Si oxide film by RIE as shown in FIG.
The upper part of the region is removed, a trench having a width of about 1 μm is formed, and the Si oxide film pattern is removed.

(2) As shown in FIG. 1 (c), after forming a silicon oxide film 15B on the side surface of the trench to a thickness of about 20 to 100 nm by thermal oxidation,
As shown in FIG. 1D, an impurity-doped Poly Si film 16 is deposited by CVD until the trench is filled.

(3) As shown in FIG. 1 (e), after removing the Poly Si film 16 deposited on the main surface of the Si oxide film 15B or more,
As shown in (f), a source contact hole 19a is formed by using a predetermined patterned resist as a mask, and the resist is removed.

(4) As shown in FIG. 1 (g), by forming an Al film on the surface and performing predetermined patterning to form a source electrode 18 and a gate electrode 19, the trench gate type vertical MOS FET of the present invention can be formed. can get.

According to the manufacturing process of the present invention, the shape of the upper portion of the gate in contact with the gate electrode is set to be longer than the trench width.
It can be an I-shape with the trench width remaining, instead of the shape.
Therefore, high integration of the element can be achieved.

In a rough approximation, space saving can be achieved only in a portion above the conventional trench width in the upper part of the trench. For example, a trench width of 1 μm and a contact hole of 2 μm
m, 1 μm between the trench and the source contact hole, and 3 μm above the conventional T-shaped trench, about 14 μm
% Space can be saved.

Further, in the cross-sectional shape around the gate contact hole before the formation of the Al film, the level difference is reduced as compared with the prior art. Therefore, after the Al film is formed, the accuracy of lithography when cutting the electrode is improved, and the accuracy of patterning the gate electrode is improved.

Next, an application example of the first embodiment will be described below. The description of the same parts as the first embodiment will be omitted. Between FIG. 1 (f) and FIG. 1 (g), as shown in FIG. 1 (h), the silicon oxide film is selectively thinly removed by using a dry etching method or a wet etching method. In the removal, the etching method is not particularly limited as long as the selectivity of the Si oxide film to the impurity-doped Poly Si film 16 is high.

According to this, it comes into contact with the gate electrode 19,
Since the surface area of the trench gate is increased, the contact of the gate can be further improved as compared with the first embodiment.

Although the present invention has been described with reference to an N-channel trench gate type vertical MOS FET in the first embodiment and the application thereof, the present invention is not limited to this. What you can do is obvious. Further, instead of the Al film, a material containing Al such as AlSi or AlSiCu may be used, and a material having a low resistance value may be used.

[0024]

Since the present invention is configured as described above, it is possible to highly integrate a trench gate type vertical MOS FET having a gate electrode wiring with reduced resistance.

[Brief description of the drawings]

1 (a) to 1 (g) are schematic cross-sectional views showing steps of manufacturing a trench gate type vertical MOSFET according to a first embodiment of the present invention. (h) is a schematic sectional view showing a characteristic manufacturing process of the semiconductor device according to the application example of the first embodiment of the present invention.

FIGS. 2A to 2H are schematic cross-sectional views showing steps of manufacturing a conventional trench gate type vertical MOS FET in which the resistance of a gate electrode wiring is reduced.

FIG. 3 is a schematic cross-sectional view showing a conventional trench gate type vertical MOS FET having a high resistance of a gate electrode wiring.

[Explanation of symbols]

10, 20 Drain layer 11, 21 Epitaxial layer 12, 22 Base region 13, 23 P ⁺ region 14, 24 Source region 15, 25 Si oxide film 16, 26 Poly Si film 18, 28 Source electrode 18a, 28a Source contact hole 19 , 29 Gate electrode 29a Gate contact hole

Claims (3)

(57) [Claims] 1. A drain region of a first conductivity type, a channel formation region of a second conductivity type formed on the drain region, and a source region formed at a predetermined interval on the channel formation region. Forming a first insulating film on a semiconductor substrate having the first insulating film, by removing an upper portion of the first insulating film, a source region, a channel forming region, and a drain region from the surface of the first insulating film; Forming a trench having a depth up to the upper part of the drain region and penetrating the source region; forming a second insulating film on a side surface of the trench; a step of covering forming a first conductive layer on the said as to fill the trench second insulating film, and after removing the first conductive layer, the second is on the first insulating film Remove one conductive layer and remove Forming a trench gate is left a portion of the first conductive layer in the wrench, to expose a predetermined portion of selectively removing the source region a predetermined portion of said first insulating film, a source contact A step of forming a hole, and selectively removing an upper surface of the first insulating film to form a first conductive film.
A step of the upper end above the main surface of the first insulating film, forming a second conductive layer, by patterning the second conductive layer, and forming a source electrode and a gate electrode A method for manufacturing a MOS type semiconductor device, comprising: 2. A drain region of a first conductivity type, a channel formation region of a second conductivity type formed on the drain region, and a source region formed at a predetermined interval on the channel formation region. A first insulating film formed on the semiconductor substrate; and a trench formed from the upper surface of the first insulating film to the source region, the channel forming region, and to the upper portion of the drain region. A second insulating film formed on a side surface of the trench; and a trench gate formed on the second insulating film so as to fill the inside of the trench to form a trench gate. A first conductive layer formed above a main surface of the first insulating film; a gate electrode formed so as to cover the upper portion of the first conductive layer; Contour formed in And a source electrode formed in the contact hole and connected to the source region. 3. The MOS type semiconductor device according to claim 2, wherein said first conductive layer is a polysilicon film.