JPS58191472A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the characteristics of an MIS transistor by a method wherein an SiO2 film is provided between a magnesia spinnel film and a semiconductor substrate. CONSTITUTION:The magnesia spinnel film 2 is epitaxially grown on the surface of a silicon substrate 1, an SiO2 film 4 is formed, and then an SiO2 film 45 is provided by performing a heat treatment in an oxidized atmosphere. A polycrystalline silicon film 5 is provided, N type impurities 6 are ion-implated, and an N type impurity region 61 is formed by performing a heat treatment. The MIS transistor is formed by providing an insulation material 47, contact hole 7 and a metal film 8. The SiO2 film 45 may be formed exceeding 100Angstrom in thickness, but as it is desirable that the gate insulating film has a large capacitance from the viewpoint of improvement in characteristics of the transistor, it is necessary that the magnesia spinner film of a high dielectric constant is thickly formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an MIg type semiconductor device, and particularly to a device with a novel structure using a single crystal insulating film as a gate insulating film.

In recent years, magnesia spinel (Mg
O・AA20. ) single-crystal insulating films can now be formed. Such magnesia spinel has a dielectric constant of 8i0□3
．． 9, it is approximately twice as large as 8 to 9, so if it is used for the gate insulating film of an MIa type semiconductor device, the capacitance can be increased.
This has the advantage that rn can be increased and the amount of charge stored in the dynamic memory can be increased.

However, at the interface between the magnesia spinel film and the silicon substrate, there is an electron capture level Nsm of approximately IQ''cIL-2, so that good device characteristics cannot be obtained.

This is because the lattice constant of magnesia spinel is 802λ and that of silicon is 5.431, and single-crystal insulating films are realized because the lattice constants are matched at double and triple lattice lengths, respectively. This is because there are many possibilities that do not involve covalent bonding.

It is an object of the present invention to provide an MIa type transistor with a novel structure that improves the above drawbacks, and the gist thereof is to provide a 4C8tO2 film between the magnesia spinel film and the semiconductor substrate.

Hereinafter, a case in which the present invention is applied to a MIS type transistor will be explained in detail, taking as an example.

FIG. 1 is a cross-sectional view illustrating the structure of an MIa type transistor. In the figure, 1 is a semiconductor substrate, 2 is a single crystal insulating film, 3 is an insulating film serving as an oxidation-resistant mask, and 4.41.42.4
5.47Fi insulating film, 5 is the first electrode, 6 is the ion flying direction, 61 is the impurity region, 7 is the contact hole, 8
respectively indicate the second electrodes.

The semiconductor substrate 1j is made of silicon having CP type conductivity, and the single crystal insulating film 2 is made of magnesia spinel to form an N-channel MIS transistor, and the manufacturing process will be explained step by step.

First, a magnesia spinel film 2 is formed on the surface of a silicon substrate 10.
is epitaxially grown (FIG. 1a).

Since the film is used as a cathode insulation film, it is rated at 100 to 1000 A, which is used in ordinary MIS transistors.
The film is formed to a desired thickness within a certain range of thickness. The epitaxial growth can be performed by transporting 1 Mg, kL as chloride using H2, HCl, CO□ gas.

Second, the surface ICBin of the magnesia spinel film 2.

After sequentially providing the film 41, followed by the nitride film 3 and the 8102 film 42, S10. The film 42 is selectively removed by a normal photoetching process to form a pattern, and then a nitride film 3.8i0□ is formed using the StO film pattern as a mask.
@41. Then, the magnesia spinel film 2 is sequentially selectively removed (FIG. 1b). The thickness of the SiO□ film 41 and 42 is 1
The thickness of the nitride film 3 is about 500 to 500X.
ooK level is preferable.

As a means for providing the 8i0□ film 41, a vapor phase growth method or a sputter deposition method is preferable.

Next, the 8102 film 4 is formed by heat treatment in an elementary atmosphere (FIG. 1C). The 5tO2 film 4 preferably has a thickness of about 0.5 to 1 micron because it is necessary for device isolation.

Next, after the 8i0□M42% nitride film 3, sto, and film 41 are sequentially removed, the 8i
A 0□ film 45 is provided (FIG. 1d). 8i0゜membrane 42
．． When removing 41, the surface of the StO□ film 4 is also removed to some extent, but since the film is thick, the amount of reduction can be ignored. A heated phosphoric acid solution is used to remove the nitride film 3, but this solution has the ability to etch magnesia spinel, and the 8i02 film 41 has the role of preventing this. 8*0
The 2 film 45 is formed as a result of oxygen diffusing in the magnesia spinel film 2 and becoming an amorphous 8102 film on the surface of the silicon substrate 1. The 8101 film 45 is provided to reduce the number of electron capture units at the interface between the magnesia spinel film 2 and the silicon substrate 1, and a film thickness of several tens to 100 λ is sufficient. 8 *
02 film 45 can be made to be more than It is necessary that the material be thick.

Next, after the polycrystalline silicon film 5 is provided, a desired pattern is formed by a normal photoetching process (1).
1), since the polycrystalline silicon film 5 is used as an electrode, it is necessary to contain impurities, and it is preferable to introduce such impurities by including them in the atmosphere at the time of film formation. After the film is formed, thermal diffusion or ion implantation may be used, and the selection is free.

Next, N-type impurities 6 such as phosphorus and arsenic are ion-implanted, followed by heat treatment to form the silicon substrate 10 (FIG. 1f).

Next, after the insulating film 47 is provided, a contact hole 7 is formed by a normal photoetching process (the first
Figure g).

Next, after a metal film 8 such as aluminum is provided, it is selectively removed by photo-etching to form an MI8 transistor (FIG. 1b).

Figure w42 is a diagram illustrating another embodiment of forming an MI8) transistor using the present invention. In the figure! The same symbols as in Figure 1 indicate substances with the same function, and 43.4
4 is an insulating film.

A semiconductor substrate IK silicon is used, and a single crystal insulating film 2 made of magnesia spinel is used to fabricate an N-channel transistor, and the manufacturing process will be explained step by step.

First, the surface of the silicon substrate 1 [810□ film 43].

Subsequently, nitride films 3 and 8i0□ films 44 are sequentially provided (FIG. 2a).

Next, a 5tO2 film 4 is formed by a normal photoetching process.
4 is selectively removed to form a desired pattern, and then using the pattern as a mask, the nitride films 3 and S10. The film 43 is sequentially selectively removed (FIG. 2b).

Next, a thick 8JO film 4 for element isolation is formed by heat treatment in an oxidizing atmosphere (FIG. 2C).

Next, 8i0. After the film 44, the nitride film 3, and the 8i0° film 43 are sequentially removed to expose a part of the surface of the silicon substrate 1, the magnesia spinel film 2 is epitaxially grown (FIG. 2d).

This tt epitaxial growth is performed on the exposed surface of the silicon substrate 1, but no polycrystalline film is formed on the surface of the StO film 4. This is due to the action of HCt gas in the epitaxial growth atmosphere.
The inventor believes that this is because the magnesia spinel above is etched.

After the structure is formed, a heat treatment in an oxidizing atmosphere results in the same structure as shown in FIG. 1d, and an MI8 transistor is then formed in the same manner as shown in FIG.

According to the present invention, the interface state Fi gate insulating film has SlO□
It is possible to use a conventional MI8) transistor with almost the same root FjLK, and the gate capacitance can be increased.
MI8) It is clear that transistor characteristics can be improved.

Further, if the present invention is applied to the MI8 capacitor of a dynamic memory, the accumulated charge density can be increased, so knot errors due to α rays can be reduced, and the pattern size can be reduced to improve the integration density.

In the above description, magnesia spinel is grown in a vapor phase on a silicon substrate, but the present invention can also be applied to a case in which sapphire is grown in a vapor phase.

[Brief explanation of the drawing]

1 shows a cross section of a semiconductor device in FIG. In the figure, l is a semiconductor substrate, 2 is a single crystal insulating film, 3 is an insulating film, 4.41.4
2, 43, 44, 45, 47 are insulating films, 5 are electrodes, 6 are ion jumping directions, 61 are impurity regions, 7 are contact holes, and 8ti electrodes. 3 Figure 1 (nu (-A/) (1) -318=

Claims (1)

[Claims] 1. A semiconductor substrate, an insulating film provided on the surface of the semiconductor substrate, a single crystal insulating film provided on the insulating film, and an electrode provided on the single crystal insulating film. MI8 composed of
A semiconductor device characterized by including a structure. 2. The semiconductor substrate is silicon and the insulating film is 8102. 2. The semiconductor device according to claim 1, wherein the single crystal insulating film is made of magnesia spinel or sapphire.