JPH0794578A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH0794578A
JPH0794578A JP20468893A JP20468893A JPH0794578A JP H0794578 A JPH0794578 A JP H0794578A JP 20468893 A JP20468893 A JP 20468893A JP 20468893 A JP20468893 A JP 20468893A JP H0794578 A JPH0794578 A JP H0794578A
Authority
JP
Japan
Prior art keywords
silicon
region
oxidation
element isolation
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP20468893A
Other languages
Japanese (ja)
Inventor
Tomoyuki Uchiyama
朋幸 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP20468893A priority Critical patent/JPH0794578A/en
Publication of JPH0794578A publication Critical patent/JPH0794578A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To restrain a thick field oxide from biting, in bird's beak, into an element forming region from the end part of an antioxidant mask, i.e., silicon nitride, when the isolation of an integrated circuit is effected by forming the field oxide selectively. CONSTITUTION:After deposition of silicon oxide 2 on a semiconductor substrate 1, silicon nitride 3 is deposited on the silicon oxide 2 in an element forming region 8. Subsequently, a field antireversion layer 4 is formed in an isolation region 7 through ion implantation followed by ion implantation 32 for rendering the silicon amorphous in the isolation region 7 using the silicon nitride 3 as a mask. In this regard, the field oxide 6 is restrained from biting, in bird's beak, into the element forming region 8 because the amorphous silicon has higher oxidation rate than single crystal silicon and the oxidation is proceeds selectively in the vertical direction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関するものであり、特にMOS型トランジスタの素子
分離層の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation layer of a MOS transistor.

【0002】[0002]

【従来の技術】従来、半導体装置、特にMOS型トラン
ジスタでは、その製造方法においてトランジスタである
素子間のフィールド領域に厚い絶縁膜を形成して素子分
離を行う選択酸化(LOCOS)法が知られている。以
下、この選択酸化法について図2(a)〜(d)を参照
して説明する。
2. Description of the Related Art Conventionally, a selective oxidation (LOCOS) method for forming a thick insulating film in a field region between elements, which is a transistor, has been known as a manufacturing method for a semiconductor device, particularly a MOS type transistor. There is. Hereinafter, this selective oxidation method will be described with reference to FIGS.

【0003】図2(a)に示すように、例えばp型(1
00)シリコン基板11上に、例えば1000℃の熱酸
化により約80nmの厚みの酸化シリコン膜12を形成
した後、化学的気相成長(CVD)法により耐酸化性
膜、例えばシリコン窒化膜13を100nm程度の厚み
に形成する。
As shown in FIG. 2A, for example, p-type (1
00) A silicon oxide film 12 having a thickness of about 80 nm is formed on the silicon substrate 11 by, for example, thermal oxidation at 1000 ° C., and then an oxidation resistant film, for example, a silicon nitride film 13 is formed by a chemical vapor deposition (CVD) method. It is formed to a thickness of about 100 nm.

【0004】次に、図2(b)に示すように、素子間の
フィールド領域21のシリコン窒化膜13を除去し、前
記フィールド領域21に自己整合で、例えばボロンのフ
ィールドイオン注入30を行い、反転防止層14を形成
する。
Next, as shown in FIG. 2B, the silicon nitride film 13 in the field region 21 between the elements is removed, and field ion implantation 30 of, for example, boron is performed in self alignment with the field region 21. The inversion prevention layer 14 is formed.

【0005】その後、図2(c)に示すように、例えば
水蒸気を含む酸化性雰囲気で1000℃、4時間程度酸
化を行い、フィールド酸化膜15をフィールド領域21
にのみ選択的に形成する。
Thereafter, as shown in FIG. 2 (c), the field oxide film 15 is oxidized in an oxidizing atmosphere containing water vapor at 1000 ° C. for about 4 hours to form the field oxide film 15 in the field region 21.
Only selectively formed.

【0006】次に、図2(d)に示すように、素子形成
領域22の酸化シリコン膜12及びシリコン窒化膜13
を除去し、素子形成領域22のシリコン基板11を露出
させる。
Next, as shown in FIG. 2D, the silicon oxide film 12 and the silicon nitride film 13 in the element forming region 22 are formed.
Are removed to expose the silicon substrate 11 in the element formation region 22.

【0007】[0007]

【発明が解決しようとする課題】従来の選択酸化法にお
いては、上述したように微細化、高密度化が進んだ集積
回路の素子分離を、選択的に形成される厚いフィールド
酸化膜15の形成によって行う際、図2(c)に示すよ
うに、酸化は素子形成領域22にも進行するため、耐酸
化性マスクであるシリコン窒化膜13の端部から厚いフ
ィールド酸化膜15が素子形成領域22に鳥のくちばし
状に食い込み(いわゆるバーズビーク)、これが高集積
化の妨げになるという問題が顕在化してきた。
According to the conventional selective oxidation method, the thick field oxide film 15 is selectively formed in the element isolation of the integrated circuit which has been miniaturized and highly densified as described above. 2C, the oxidation proceeds to the element formation region 22 as well, so that the thick field oxide film 15 is formed on the element formation region 22 from the end of the silicon nitride film 13 which is an oxidation resistant mask. A problem has emerged in which the bird's beak-like bite (the so-called bird's beak) interferes with high integration.

【0008】そこで、本発明の目的は、フィールド領域
にフィールド酸化膜を形成する際に、フィールド酸化膜
が素子形成領域に鳥のくちばし状に食い込むことを抑制
することにある。
Therefore, an object of the present invention is to suppress the bird's beak-like bite of the field oxide film in the element formation region when the field oxide film is formed in the field region.

【0009】[0009]

【課題を解決するための手段】前記目的を達成するた
め、本発明の半導体装置の製造方法は、半導体基板上に
酸化膜を形成する工程と、素子形成領域の前記酸化膜上
に耐酸化性物質を形成する工程と、素子分離領域にフィ
ールド反転防止層を形成する工程と、前記耐酸化性物質
をマスクとして素子分離領域の半導体基板内にイオン注
入する工程と、熱酸化により素子分離領域にフィールド
酸化膜を形成する工程と、前記耐酸化性物質を除去する
工程とからなる。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an oxide film on a semiconductor substrate and an oxidation resistance on the oxide film in an element formation region. A step of forming a substance, a step of forming a field inversion prevention layer in the element isolation region, a step of implanting ions into the semiconductor substrate of the element isolation region using the oxidation resistant material as a mask, and a step of thermally oxidizing the element isolation region. It comprises a step of forming a field oxide film and a step of removing the oxidation resistant material.

【0010】また、前記耐酸化性物質をマスクとして素
子分離領域の半導体基板内にイオン注入する工程は、シ
リコン、酸素、窒素、ネオン、アルゴン、クリプトン、
キセノンのうちのいずれかの元素をイオン注入すること
が好ましい。
In the step of implanting ions into the semiconductor substrate in the element isolation region using the oxidation resistant material as a mask, silicon, oxygen, nitrogen, neon, argon, krypton,
It is preferable to ion-implant any element of xenon.

【0011】また、前記耐酸化性物質をマスクとして素
子分離領域の半導体基板内にイオン注入する工程は、イ
オン注入のドーズ量を1×1014cm-2以上とすること
が好ましい。
Further, in the step of implanting ions into the semiconductor substrate in the element isolation region using the oxidation resistant material as a mask, the dose amount of ion implantation is preferably 1 × 10 14 cm -2 or more.

【0012】[0012]

【作用】例えば、シリコンは1×1014cm-2以上のド
ーズ量でイオン注入を行うとアモルファスになる。アモ
ルファスシリコンにおける酸化種の拡散係数は単結晶中
における拡散係数より大きいので、同じ酸化時間で比較
した場合、アモルファスシリコンの方が効率良く酸化反
応が進む。従って、同じ膜厚のLOCOSを得ようとす
る場合、単結晶シリコンよりもアモルファスシリコンの
方が酸化時間を短縮できる。すなわち、素子分離領域に
フィールド酸化膜を形成する前に、素子分離領域の半導
体基板内にイオン注入を行ってアモルファス化すること
により、素子形成領域への鳥のくちばし状の食い込みも
小さくなる。
FUNCTION For example, silicon becomes amorphous when ion implantation is performed with a dose amount of 1 × 10 14 cm -2 or more. Since the diffusion coefficient of the oxidizing species in the amorphous silicon is larger than that in the single crystal, when compared with the same oxidation time, the oxidation reaction proceeds more efficiently in the amorphous silicon. Therefore, in order to obtain LOCOS having the same film thickness, amorphous silicon can reduce the oxidation time more than single crystal silicon. That is, before the field oxide film is formed in the element isolation region, ion implantation into the semiconductor substrate in the element isolation region to make it amorphous makes the beak-like bite of the bird into the element formation region small.

【0013】[0013]

【実施例】図1を用いて本発明の一実施例を説明する。
図1は実施例による選択酸化法を工程順に示した断面図
である。
Embodiment An embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a cross-sectional view showing the selective oxidation method according to the embodiment in the order of steps.

【0014】図1(a)に示すように、p型(100)
シリコン基板1を、例えば1000℃の熱酸化により約
80nmの厚みの酸化シリコン膜2を形成した後、化学
的気相成長(CVD)法により耐酸化性膜、例えばシリ
コン窒化膜3を100nm程度の厚みに形成する。
As shown in FIG. 1A, p-type (100)
After forming a silicon oxide film 2 having a thickness of about 80 nm on the silicon substrate 1 by thermal oxidation at 1000 ° C., an oxidation resistant film, for example, a silicon nitride film 3 having a thickness of about 100 nm is formed by a chemical vapor deposition (CVD) method. Form to thickness.

【0015】次に、図1(b)に示すように、フィール
ド領域7のシリコン窒化膜3を除去し、フィールド領域
7に自己整合で、例えばドーズ量3×1011cm-2のボ
ロンのフィールドイオン注入31を行い、反転防止層4
を形成する。
Next, as shown in FIG. 1B, the silicon nitride film 3 in the field region 7 is removed and self-aligned with the field region 7, for example, a boron field having a dose amount of 3 × 10 11 cm -2. Ion implantation 31 is performed, and the inversion prevention layer 4 is formed.
To form.

【0016】その後、図1(c)に示すように、アモル
ファス化のためのイオン注入32をイオン種が酸素、ド
ーズ量が3×1015cm-2、加速電圧が150keVの
条件で行い、アモルファス層5を形成する。ここでアモ
ルファスシリコンの酸化速度は単結晶シリコンのそれと
比較して大きいことが知られている。本実施例のように
素子分離領域7にアモルファス化のためのイオン注入3
2を行うと、イオンビームの直進性のため、基板のアモ
ルファス化は素子分離領域7においてのみ進み、マスク
となるシリコン窒化膜3下部はアモルファス化されな
い。
Thereafter, as shown in FIG. 1C, ion implantation 32 for amorphization is performed under the conditions of oxygen as an ion species, a dose amount of 3 × 10 15 cm -2 , and an acceleration voltage of 150 keV. Form layer 5. Here, it is known that the oxidation rate of amorphous silicon is higher than that of single crystal silicon. Ion implantation 3 for amorphization into the element isolation region 7 as in the present embodiment
When the step 2 is performed, the substrate becomes amorphous only in the element isolation region 7 due to the straightness of the ion beam, and the lower portion of the silicon nitride film 3 serving as a mask is not made amorphous.

【0017】次に、図1(d)に示すように、水蒸気を
含む酸化性雰囲気で1000℃、3時間の酸化を行いフ
ィールド酸化膜6を形成する。この様に、フィールド酸
化を行うとアモルファス層5の酸化速度は単結晶シリコ
ンの酸化速度に比べて大きいことにより、縦方向の酸化
が選択的に進行する。従って、従来の単結晶シリコンを
酸化する方法に比べ酸化時間を短縮できるので、素子形
成領域8の横方向の鳥のくちばし状の食い込みが抑制さ
れる。
Next, as shown in FIG. 1D, the field oxide film 6 is formed by performing oxidation at 1000 ° C. for 3 hours in an oxidizing atmosphere containing water vapor. As described above, when the field oxidation is performed, the oxidation rate of the amorphous layer 5 is higher than the oxidation rate of the single crystal silicon, so that the vertical oxidation selectively progresses. Therefore, the oxidation time can be shortened as compared with the conventional method of oxidizing single crystal silicon, so that the bird's beak-like bite in the lateral direction of the element formation region 8 is suppressed.

【0018】次に、図1(e)に示すように、素子形成
領域8の酸化シリコン膜2及びシリコン窒化膜3を除去
し、素子形成領域8のシリコン基板1を露出させる。
Next, as shown in FIG. 1E, the silicon oxide film 2 and the silicon nitride film 3 in the element forming region 8 are removed to expose the silicon substrate 1 in the element forming region 8.

【0019】なお、通常のフィールド酸化前に行う反転
防止のための不純物イオン注入31におけるドーズ量は
1011〜1012cm-2程度であり、半導体基板1の結晶
性を変化させるほどの量ではないので、上記の作用はな
い。
The dose amount in the impurity ion implantation 31 for preventing inversion which is usually performed before field oxidation is about 10 11 to 10 12 cm −2, which is an amount enough to change the crystallinity of the semiconductor substrate 1. Since it does not exist, the above effect does not occur.

【0020】また、イオン注入を行うことにより、ある
値以上のドーズ量で被イオン注入物の結晶性が失われる
ことは広く知られており、例えばシリコンではこのドー
ズ量の値は室温で約1014cm-2である。
It is widely known that the ion implantation causes the crystallinity of the ion-implanted material to be lost at a dose amount higher than a certain value. For example, in silicon, the dose amount value is about 10 at room temperature. It is 14 cm -2 .

【0021】なお、本実施例では、反転防止用のイオン
注入31をアモルファス化のためのイオン注入32に先
行させたが、アモルファス化のためのイオン注入32を
反転防止用のイオン注入31に先行させてもよい。
In this embodiment, the ion implantation 31 for preventing inversion precedes the ion implantation 32 for amorphization, but the ion implantation 32 for amorphization precedes the ion implantation 31 for prevention of inversion. You may let me.

【0022】本実施例では、イオン種として酸素を用い
たが、フィールド領域7のシリコン基板1をアモルファ
ス化させれば同様の効果が得られるので、酸素以外にシ
リコン、窒素、ネオン、アルゴン、クリプトン、キセノ
ンを用いてもよい。
Although oxygen is used as the ion species in this embodiment, the same effect can be obtained by making the silicon substrate 1 in the field region 7 amorphous. Therefore, in addition to oxygen, silicon, nitrogen, neon, argon, and krypton are used. Alternatively, xenon may be used.

【0023】[0023]

【発明の効果】以上説明したように、本発明によれば、
選択酸化法によって生じる素子形成領域への鳥のくちば
し状の食い込みを効果的に抑制することができ、半導体
装置の歩留り及び設計マージンの向上に寄与することが
できる。
As described above, according to the present invention,
The bird's beak-shaped bite into the element formation region caused by the selective oxidation method can be effectively suppressed, and the yield and design margin of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による素子分離領域の選択酸
化法を工程順に示す断面図である。
FIG. 1 is a cross-sectional view showing a method of selectively oxidizing an element isolation region according to an embodiment of the present invention in the order of steps.

【図2】従来法による素子分離領域の選択酸化法を工程
順に示す断面図である。
FIG. 2 is a cross-sectional view showing, in the order of steps, a selective oxidation method for an element isolation region according to a conventional method.

【符号の説明】[Explanation of symbols]

1 p型シリコン基板 2 シリコン酸化膜 3 シリコン窒化膜 4 反転防止層 5 アモルファス層 6 フィールド酸化膜 7 フィールド領域 8 素子形成領域 31 反転防止用のイオン注入 32 アモルファス化のためのイオン注入 1 p-type silicon substrate 2 silicon oxide film 3 silicon nitride film 4 inversion prevention layer 5 amorphous layer 6 field oxide film 7 field region 8 element formation region 31 ion implantation for inversion prevention 32 ion implantation for amorphization

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に酸化膜を形成する工程
と、 素子形成領域の前記酸化膜上に耐酸化性物質を形成する
工程と、 素子分離領域にフィールド反転防止層を形成する工程
と、 前記耐酸化性物質をマスクとして素子分離領域の半導体
基板内にイオン注入する工程と、 熱酸化により素子分離領域にフィールド酸化膜を形成す
る工程と、 前記耐酸化性物質を除去する工程とを備えたことを特徴
とする半導体装置の製造方法。
1. A step of forming an oxide film on a semiconductor substrate, a step of forming an oxidation resistant material on the oxide film in an element formation region, and a step of forming a field inversion prevention layer in an element isolation region, A step of implanting ions into the semiconductor substrate of the element isolation region using the oxidation resistant material as a mask; a step of forming a field oxide film in the element isolation area by thermal oxidation; and a step of removing the oxidation resistant material. A method for manufacturing a semiconductor device, comprising:
【請求項2】 前記耐酸化性物質をマスクとして素子分
離領域の半導体基板内にイオン注入する工程は、シリコ
ン、酸素、窒素、ネオン、アルゴン、クリプトン、キセ
ノンのうちのいずれかの元素をイオン注入することを特
徴とする請求項1記載の半導体装置の製造方法。
2. The step of ion-implanting into the semiconductor substrate of the element isolation region using the oxidation resistant material as a mask, ion-implanting any element of silicon, oxygen, nitrogen, neon, argon, krypton, and xenon. The method for manufacturing a semiconductor device according to claim 1, wherein
【請求項3】 前記耐酸化性物質をマスクとして素子分
離領域の半導体基板内にイオン注入する工程は、イオン
注入のドーズ量を1×1014cm-2以上とすることを特
徴とする請求項1記載の半導体装置の製造方法。
3. The step of implanting ions into the semiconductor substrate in the element isolation region using the oxidation resistant material as a mask has a dose amount of ion implantation of 1 × 10 14 cm −2 or more. 1. The method for manufacturing a semiconductor device according to 1.
JP20468893A 1993-07-27 1993-07-27 Fabrication of semiconductor device Withdrawn JPH0794578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20468893A JPH0794578A (en) 1993-07-27 1993-07-27 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20468893A JPH0794578A (en) 1993-07-27 1993-07-27 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0794578A true JPH0794578A (en) 1995-04-07

Family

ID=16494666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20468893A Withdrawn JPH0794578A (en) 1993-07-27 1993-07-27 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0794578A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001008208A1 (en) * 1999-07-26 2001-02-01 Tadahiro Ohmi Semiconductor device, method for forming silicon oxide film, and apparatus for forming silicon oxide film
JP2008177571A (en) * 1999-07-26 2008-07-31 Foundation For Advancement Of International Science Method of forming silicon oxide layer, semiconductor device and method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001008208A1 (en) * 1999-07-26 2001-02-01 Tadahiro Ohmi Semiconductor device, method for forming silicon oxide film, and apparatus for forming silicon oxide film
US6677648B1 (en) 1999-07-26 2004-01-13 Tadahiro Ohmi Device having a silicon oxide film containing krypton
KR100577869B1 (en) * 1999-07-26 2006-05-10 다다히로 오미 Semiconductor device, method for forming silicon oxide film, and apparatus for forming silicon oxide film
US7268404B2 (en) 1999-07-26 2007-09-11 Tadahiro Ohmi Device having a silicon oxide film containing krypton
US7279066B2 (en) 1999-07-26 2007-10-09 Tadahiro Ohmi Apparatus for forming silicon oxide film
JP2008177571A (en) * 1999-07-26 2008-07-31 Foundation For Advancement Of International Science Method of forming silicon oxide layer, semiconductor device and method of manufacturing the same
US7491656B2 (en) 1999-07-26 2009-02-17 Foundation For Advancement Of International Science Semiconductor device, method for forming silicon oxide film, and apparatus for forming silicon oxide film

Similar Documents

Publication Publication Date Title
US6900092B2 (en) Surface engineering to prevent epi growth on gate poly during selective epi processing
JP2982383B2 (en) Method for manufacturing CMOS transistor
JP3127455B2 (en) Semiconductor device manufacturing method
JP2925008B2 (en) Method for manufacturing semiconductor device
JPH0794578A (en) Fabrication of semiconductor device
JP3328600B2 (en) Fabrication process for bipolar and BICMOS devices
KR100223736B1 (en) Method of manufacturing semiconductor device
KR100200184B1 (en) Manufacturing method of semiconductor device
JPH0982812A (en) Manufacture of semiconductor device
JP2002026317A (en) Semiconductor device and manufacturing method thereof
US6545328B1 (en) Semiconductor device
JP2513312B2 (en) Method for manufacturing MOS transistor
JPS60124972A (en) Manufacture of semiconductor device
JP3043791B2 (en) Method for manufacturing semiconductor device
JP4940514B2 (en) Manufacturing method of semiconductor device
JP3110313B2 (en) Method for manufacturing semiconductor device
JPS628028B2 (en)
JPH01245560A (en) Manufacture of semiconductor device
JPH08130305A (en) Manufacture of semiconductor device
JP2546650B2 (en) Method of manufacturing bipolar transistor
JPS63217655A (en) Manufacture of semiconductor device
JPH10107281A (en) Semiconductor device and its manufacture
JPS628029B2 (en)
JPH08241930A (en) Manufacture of semiconductor device
JPH0590574A (en) Semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20001003