JPS5818950A - Multilayer wiring substrate - Google Patents
Multilayer wiring substrateInfo
- Publication number
- JPS5818950A JPS5818950A JP11707281A JP11707281A JPS5818950A JP S5818950 A JPS5818950 A JP S5818950A JP 11707281 A JP11707281 A JP 11707281A JP 11707281 A JP11707281 A JP 11707281A JP S5818950 A JPS5818950 A JP S5818950A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- substrate
- pads
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Abstract
Description
【発明の詳細な説明】
本発明は、多層配線基板に関し、特に修正布線と基本配
線パターン間の信号漏洩を少なくすることができる多層
配線基板の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board, and more particularly to a structure of a multilayer wiring board that can reduce signal leakage between corrected wiring and basic wiring patterns.
従来、ＬＳＩパッケージとしては、印刷配線板が用いら
れ、配線に誤シが発見された場合若しくは配線の変更が
必要になった場合には、所望の修正布線を外付けＫよっ
て接続していた。しかし、近年のコンビーータの中央処
理装置等に実装されるＬＳＩパッケージにおいては、処
理速度の高速化のｌ！ｄｌｌから、平均布線長を短くす
る九め実装の高密度化が図られておシ、修正布線をすべ
て外付は布４１によって行なうのに必要な空間的余裕が
無くなっている。このため、修シー榴線の一部をあらか
じめ配線基板中く形成しておく必要が生じている。しか
し、同一基板中に基本配線パターンと修正布線を形成す
ると、修正布線と基本配線パターン間の信号漏洩が生じ
るおそれがある。Ｓ上布線と基本配線パターンとの間に
信号漏洩があると、誤動作等の原因になるから不都合で
ある。Conventionally, printed wiring boards have been used for LSI packages, and when an error is discovered in the wiring or when it is necessary to change the wiring, the desired corrected wiring is connected using an external K. . However, in recent years, LSI packages installed in the central processing units of converters, etc. have been designed to increase processing speed. dll to shorten the average wiring length, and the space necessary to carry out all correction wiring externally using the cloth 41 is no longer available. For this reason, it has become necessary to form a portion of the repair wire in advance in the wiring board. However, if the basic wiring pattern and the modified wiring are formed on the same board, there is a risk that signal leakage will occur between the modified wiring and the basic wiring pattern. If there is signal leakage between the S upper wiring and the basic wiring pattern, it is inconvenient because it may cause malfunctions.
本発明の目的は、基本配線パターンとの信号漏洩の少な
い修正布線を、あらかじめ多層配線基板中に形成し、修
正が容易で高速高密度実装可能な多層配線基板を提供す
ることにある。An object of the present invention is to provide a multilayer wiring board in which correction wiring with little signal leakage from the basic wiring pattern is formed in advance in the multilayer wiring board, and correction is easy and high-speed, high-density mounting is possible.
本発明の配線基板は、基板の一辺に平行な配線パターン
および直角な配線パターンを有する多１−配線基板にお
いて、基板の一辺に対して４５°の方向に修正布線パタ
ーンを形成し、該修正布線パターンの端部を基板表面に
露出させたことを特徴とする。The wiring board of the present invention is a multi-wiring board having a wiring pattern parallel to one side of the board and a wiring pattern perpendicular to one side of the board. A feature is that the ends of the wiring pattern are exposed on the substrate surface.
次に、本発明について、＃Ａ面を参照して詳細に説明す
る。Next, the present invention will be described in detail with reference to side #A.
！１図は、本発明の一実施例を示す平面図であシ、第２
図はそのＡ−Ａ断面図である。すなわち、セラぐツク基
板１０上には、基本配線パターンにニジ基本配＠２１お
よび２２が多層に形成されている。各層の配線間は勿論
絶縁層２８によって絶縁されており一また必要個所にお
いて層間接続導体２４によって接続されている。配線２
１は図中左右方向に延びた配線であシ、配線２２は図中
前後方向の配線であシ相互に直交している。以上は、従
来の多層配線と同様であり、簡単のため第１図には示さ
れていない。そして、上述の基本配線パターンの上層に
修正布線パターン８１を形成する。! Figure 1 is a plan view showing one embodiment of the present invention.
The figure is a sectional view taken along line A-A. That is, on the ceramic substrate 10, the basic wiring patterns 21 and 22 are formed in multiple layers. The wiring in each layer is of course insulated by an insulating layer 28 and connected at necessary locations by interlayer connection conductors 24. Wiring 2
Wires 1 extend in the left-right direction in the figure, and wires 22 extend in the front-rear direction in the figure and are orthogonal to each other. The above is similar to conventional multilayer wiring, and is not shown in FIG. 1 for simplicity. Then, a modified wiring pattern 81 is formed on the upper layer of the basic wiring pattern described above.
修正布線パターン３１は、第１図から理解されるように
上述の基本配線パターンに対して４６°の角Ｉをなす方
向（直交する２つの方向が存在する）に形成されている
。そして、基板表面上のＬＳＩ接着パッド４２およびそ
の周囲に配されたＬＳＩ接伏パッド４１のない領域テ、
紡記修正布線パターン８１の端部を露出させパッド８２
を形成する。As understood from FIG. 1, the modified wiring pattern 31 is formed in a direction forming an angle I of 46° with respect to the above-mentioned basic wiring pattern (there are two orthogonal directions). Then, an area where there is no LSI adhesive pad 42 on the substrate surface and no LSI contact pad 41 arranged around it,
The end of the spinning correction wiring pattern 81 is exposed and the pad 82 is attached.
form.
本実施例では、ｅ鎌層２８の該轟領域に凹部を形成する
ことによって修正布縁パターン８１と同一平面上にパッ
ド８２ｔ−形成しているが、このような凹部を設けない
で、パッド８怠を表ＩｉＫ形成し。In this embodiment, the pad 82t- is formed on the same plane as the corrected fabric edge pattern 81 by forming a recess in the area of the e-sickle layer 28, but the pad 82t- is formed on the same plane as the modified cloth edge pattern 81. Form a table IiK.
層間接続導体によりて修正布縁８１と接続してもよい、
その場合は、修正布縁パターン８１Ｆｉ、必ずしも基本
配線パターン２１，８ｇの上層に形成しなくてもよい、
すなわち、下層部又は中間４ＶＣ形成することも可能で
ある。修正有線パターンは全部の修正布縁を形成する４
のではなく、上記パッド８２相互関又は、上記パッド８
Ｂと紡記パッド４１間を外付は付線８８によりて適宜接
続することＫより修正を完成する。しかし、修正布縁８
１が例えば金ペーストを印刷焼成し九厚狭又は選択金め
つき法′７＃ＩＩ膜等によつて高密度に形成されている
ため、僅かな外付は布１１＄８の接続によって修正を完
成することができる６ｔた、そのために必要な領域は僅
かでよいから、ＬＳＩ接着パッドおよびＬＳＩ接続パッ
ド等の領域の間隙を使用することで足シる。従って、Ｌ
ＳＩの搭載密度を減少することはない。まえ、上記修正
４酬ａｘは、基本配線２１．２２等に対して４６°の角
度で形成されているから、両配線が長区間平行すること
がないため、その間の信号漏洩は極めて少ない。なお、
上述の絶縁層２８は、従来と同様に、ガラス若しくはセ
ラばツクを主成分とする絶縁ペースト又は有機高分子材
料により形成される。ままた、外付は布＃８８８は、パ
ッド８２が金の場合には、金線を用いて熱圧着によシ接
続し、パッド８２が鋼の場合には、鋼線を用いてハンダ
付けすれば良い。It may be connected to the modified cloth edge 81 by an interlayer connection conductor.
In that case, the modified cloth edge pattern 81Fi does not necessarily have to be formed on the upper layer of the basic wiring patterns 21 and 8g.
That is, it is also possible to form 4VC in the lower layer or in the middle. The modified wire pattern forms the entire modified cloth border 4
rather than the pad 82 mutually or the pad 8
The correction is completed by connecting B and the spinning pad 41 as appropriate with external attached wires 88. However, the modified cloth edge 8
1 is formed in a high density by printing and firing gold paste and using 9 thickness/narrow or selective gold plating method '7#II film, etc., so slight external attachments are completed by connecting cloth 11$8. However, since only a small area is required for this purpose, space can be saved by using gaps between areas such as LSI bonding pads and LSI connection pads. Therefore, L
SI loading density will not be reduced. First, since the modified four wires ax are formed at an angle of 46° with respect to the basic wirings 21, 22, etc., the two wirings are not parallel to each other for a long period of time, so that there is extremely little signal leakage between them. In addition,
The above-mentioned insulating layer 28 is formed of an insulating paste or an organic polymer material whose main component is glass or ceramics, as in the conventional case. In addition, for the external cloth #888, if the pad 82 is made of gold, it is connected by thermocompression using a gold wire, and if the pad 82 is made of steel, it is connected by soldering using a steel wire. Good.
以上のように、本発明においては、基本配線パターンと
４６°の角度をなす修正布線パターンを形成し、かつ、
その端部を基板表面のＬＳＩ接続パッド等のない領域に
露出させた構造であるから、修正布線パターンの端部相
互間又は、該熾部とＬＳＩ接続パッド間等を少数の外付
は布線で接続することＫより容易に修正布線を完成させ
ることが可能であり、そのためにＬＳＩの搭載密度を減
少させることなく、しかも修正布線と基本配線間の信号
漏洩を生じさせないという効果を有する。As described above, in the present invention, a modified wiring pattern is formed at an angle of 46° with the basic wiring pattern, and
Since the structure has its ends exposed in areas where there are no LSI connection pads, etc. on the surface of the board, a small number of external wires can be placed between the ends of the corrected wiring pattern or between the edges and the LSI connection pads. It is possible to complete the modified wiring more easily than by connecting with wires, and therefore, it is possible to complete the modified wiring without reducing the LSI mounting density, and also has the effect of not causing signal leakage between the modified wiring and the basic wiring. have
８１図は本発明の一実施例を示す平面図、第２図はその
Ａ−Ａ断面図である。
図において、１Ｇ・・・七クイック基板、２１．２２・
・・基本配線、２８・・・絶縁層、２４・・・層間接続
導体、８１・・・修正布線、８２・・・パッド、８８・
・・外付は付線、４１・・・ＬＳＩ接続パッド、４ト・
・ＬＳ Ｉｍ層パッド。
代理人 弁理士住田俊宗FIG. 81 is a plan view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA. In the figure, 1G...7 quick board, 21.22.
...Basic wiring, 28...Insulating layer, 24...Interlayer connection conductor, 81...Correction wiring, 82...Pad, 88...
... External wires, 41... LSI connection pad, 4 to...
・LS Im layer pad. Agent: Patent attorney Toshimune Sumita
Claims (1)
ーンを有する多層配線基板において、基板の一辺に対し
て４６°の方向に修正布線パターンを形成し、該修正布
線パターンの端部を基板表面に露出させたことを特徴と
する多層配線基板。In a multilayer wiring board having a wiring pattern parallel to one side of the board and a wiring pattern perpendicular to one side of the board, a corrected wiring pattern is formed in a direction of 46 degrees to one side of the board, and the end of the corrected wiring pattern is attached to the board surface. A multilayer wiring board characterized by being exposed to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11707281A JPS5818950A (en) | 1981-07-28 | 1981-07-28 | Multilayer wiring substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11707281A JPS5818950A (en) | 1981-07-28 | 1981-07-28 | Multilayer wiring substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5818950A true JPS5818950A (en) | 1983-02-03 |
| JPH0125228B2 JPH0125228B2 (en) | 1989-05-16 |
Family
ID=14702711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11707281A Granted JPS5818950A (en) | 1981-07-28 | 1981-07-28 | Multilayer wiring substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818950A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6135578A (en) * | 1984-07-27 | 1986-02-20 | Agency Of Ind Science & Technol | Connection of superconductive circuit |
| JPH0196953A (en) * | 1987-09-25 | 1989-04-14 | Internatl Business Mach Corp <Ibm> | Wiring structure |
| US5177594A (en) * | 1991-01-09 | 1993-01-05 | International Business Machines Corporation | Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55108797A (en) * | 1979-02-13 | 1980-08-21 | Hitachi Ltd | Circuit board |
| JPS567457A (en) * | 1979-06-29 | 1981-01-26 | Ibm | Package for semiconductor device |
-
1981
- 1981-07-28 JP JP11707281A patent/JPS5818950A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55108797A (en) * | 1979-02-13 | 1980-08-21 | Hitachi Ltd | Circuit board |
| JPS567457A (en) * | 1979-06-29 | 1981-01-26 | Ibm | Package for semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6135578A (en) * | 1984-07-27 | 1986-02-20 | Agency Of Ind Science & Technol | Connection of superconductive circuit |
| JPH0428154B2 (en) * | 1984-07-27 | 1992-05-13 | Kogyo Gijutsu Incho | |
| JPH0196953A (en) * | 1987-09-25 | 1989-04-14 | Internatl Business Mach Corp <Ibm> | Wiring structure |
| US5177594A (en) * | 1991-01-09 | 1993-01-05 | International Business Machines Corporation | Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0125228B2 (en) | 1989-05-16 |
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