JPH0428154B2 - - Google Patents
Info
- Publication number
- JPH0428154B2 JPH0428154B2 JP59155277A JP15527784A JPH0428154B2 JP H0428154 B2 JPH0428154 B2 JP H0428154B2 JP 59155277 A JP59155277 A JP 59155277A JP 15527784 A JP15527784 A JP 15527784A JP H0428154 B2 JPH0428154 B2 JP H0428154B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- superconducting
- circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 22
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 description 43
- 239000010410 layer Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 229910000978 Pb alloy Inorganic materials 0.000 description 5
- 229910000846 In alloy Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- -1 Josephson junctions Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/85—Superconducting active materials
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、超電導性を利用した計算回路に係
り、とくに集積回路の高密度実装化を行なうのに
好適な集積回路の搭載法および集積回路間の結線
法に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a calculation circuit using superconductivity, and in particular to a method of mounting an integrated circuit suitable for high-density packaging of integrated circuits and a method of mounting an integrated circuit between integrated circuits. This is related to the wiring method.
従来の超電導集積回路チツプの実装方法に関し
ては、所定の寸法に切断された集積回路チツプを
チツプキヤリア上に搭載し、チツプとチツプキヤ
リア間の電気的接続については超電導性を有する
Pb合金の厚膜を介して、チツプのパツドからチ
ツプキヤリアに連結する方法が用いられている
（H.C.Jones and D.J.Herrell，IBM J.of Res.
and Dev.Vol.24，P172，1980）。この超電導回路
の実装方法における問題点はパツド部分における
接続に対する信頼性の問題である。数百〜数千ゲ
ートの高集積論理回路においては、チツプあたり
100個前後のパツドが必要である。このような配
線の接続方法において、欠陥無く、多数のパツド
を電気的に接続することはきわめて困難である。
さらに、このような接続方法においては、接続部
におけるインピーダンスのミスマツチの問題、さ
らには、全体的な高密度集積化に対する制約があ
る。
Regarding the conventional method of mounting superconducting integrated circuit chips, an integrated circuit chip cut to predetermined dimensions is mounted on a chip carrier, and electrical connections between the chip and the chip carrier are made using superconducting properties.
A method of connecting the chip pad to the chip carrier via a thick film of Pb alloy has been used (HCJones and DJHerrell, IBM J.of Res.
and Dev.Vol.24, P172, 1980). The problem with this superconducting circuit mounting method is the reliability of the connection at the pad portion. In highly integrated logic circuits with hundreds to thousands of gates, the
Approximately 100 pads are required. In such a wiring connection method, it is extremely difficult to electrically connect a large number of pads without defects.
Furthermore, such a connection method has the problem of impedance mismatch at the connection portion, and furthermore, there are restrictions on overall high-density integration.
本発明は超電導集積回路の実装技術に関して、
高密度集積回路の相互配線を可能にし、かつ信頼
性の高い集積回路間の接続方法を与えるものであ
る。
The present invention relates to mounting technology for superconducting integrated circuits,
The present invention enables interconnection of high-density integrated circuits and provides a highly reliable connection method between integrated circuits.
本発明においては、超電導集積回路間の接続方
法に関して、個々の独立した集積回路を同一基板
上に形成し、これらの集積回路間の結線を、基板
上に形成した超電導膜配線によつて行なう。この
配線は集積回路内で用いる超電導層と同一の超電
導層を１層あるいは２層用いて、格子状に配す
る。２層以上の場合、配線は互に層間絶縁膜を介
して絶縁される。（超電導多層構造）超電導配線
用の材料はNb、あるいはNb3SnなどNbを主成分
として含有する超電導材料とする。格子増配線列
の交点における配線の接続は以下のようにして行
う。つまり、接続を必要とする配線間を、Pbを
主成分とする合金膜によつて接続する。交点にお
いて配線の接続が２ケ所になる場合は、第１層目
のPb合金接続後、層間絶縁膜を形成し、この上
から、第２層目のPb合金膜を形成することによ
り接続を行う。
In the present invention, regarding a method for connecting superconducting integrated circuits, individual independent integrated circuits are formed on the same substrate, and connections between these integrated circuits are performed by superconducting film wiring formed on the substrate. The wiring is arranged in a grid pattern using one or two layers of the same superconducting layer as used in the integrated circuit. In the case of two or more layers, the wirings are insulated from each other via an interlayer insulating film. (Superconducting multilayer structure) The material for superconducting wiring is Nb or a superconducting material containing Nb as a main component, such as Nb 3 Sn. The wiring connections at the intersections of the lattice expansion wiring arrays are performed as follows. In other words, interconnects that require connection are connected using an alloy film containing Pb as a main component. If there are two wiring connections at the intersection, connect the first layer of Pb alloy, form an interlayer insulating film, and then form the second layer of Pb alloy film on top of this. .
以下、本発明を実施例を参照して詳細に説明す
る。超電導回路はジヨセフソン接合をスイツチン
グ素子とし、電流を直接ゲートに注入することに
よりスイツチング動作を行なわせる、いわゆる電
流注入直接結合型回路を基本ゲートとする論理回
路とした。回路の種類は直接結合型論理ゲートを
直列に配列した鎖状回路とした。１回路当りの占
有面積は2.5mm角とした。１回路の領域は従来の
回路チツプ同じく、周辺に100μｍ×100μｍの面
積を有するパツド電極を配列することにより決め
られる。回路内の配線は２層の超電導膜によつて
形成されるが、同時に回路と回路間に格子状に２
次元的な配線を行なう。一方向の配線の端部は回
路パツドに接続される。２インチのシリコンウエ
ハ上に、上に述べた論理ゲート10段分の鎖状回路
を１個含んだ回路を４個並べた。これらの回路の
間のパツド列に平行な配線は２本である。超電導
回路は磁気遮蔽を兼ねるグランドプレーン膜、抵
抗膜、２層の超電導配線膜とジヨセフソン接合と
層間絶縁膜から構成される。ジヨセフソン接合の
電極を形成する超電導膜は配線と同一の超電導層
が用いられる。グランドプレーン膜はNb膜、抵
抗膜はMo膜、ジヨセフソン接合の下部電極膜は
Nb膜、上部電極膜はPb・In合金膜、層間絶縁膜
はSiO膜とした。各集積回路を完成した段階で、
回路間に交差する配線格子が存在するが、この配
線格子はしたがつて、ジヨセフソン接合下部電極
膜に用いたNb膜である。インピーダンスのマツ
チングをとるために、回路間の配線領域にもグラ
ンドプレーン膜を敷く。層間絶縁膜はSiO膜であ
る。隣接する各鎖増回路どうしを互に直列に接続
し、１個のウエハ上で40段分の鎖状回路とした
が、これは以下の方法で行つた。第１図に示すよ
うに配線の交差点において、層間絶縁膜に矩形の
窓１を開く。各配線２，３の一部を窓の内部にま
で入れるが、互に接触しない範囲に留めておく。
次にレジスト膜のパターン形成工程および、
Pb・In膜の成膜工程およびリフトオフ工程を通
じて、図に示すような配線間の接続膜４を形成す
る。このような工程を通じて、第２図に示すよう
に、直結型鎖状回路５間の直列接続を配線２，３
および配線接続６を用いることにより完成した。
図において入力信号は配線７より入り、出力新は
配線８より取出される。
Hereinafter, the present invention will be explained in detail with reference to Examples. The superconducting circuit uses a Josephson junction as a switching element, and a logic circuit whose basic gate is a so-called current injection direct coupling circuit, which performs switching operation by directly injecting current into the gate. The type of circuit was a chain circuit in which directly coupled logic gates were arranged in series. The area occupied by one circuit was 2.5 mm square. As with conventional circuit chips, the area of one circuit is determined by arranging pad electrodes having an area of 100 .mu.m.times.100 .mu.m around the periphery. The wiring in the circuit is formed by two layers of superconducting film, but at the same time, two layers are formed in a lattice pattern between the circuits.
Perform dimensional wiring. The ends of the wires in one direction are connected to circuit pads. On a 2-inch silicon wafer, four circuits, each containing one chain circuit for the 10 stages of logic gates mentioned above, were arranged. There are two wires parallel to the pad rows between these circuits. The superconducting circuit is composed of a ground plane film that also serves as a magnetic shield, a resistive film, two layers of superconducting wiring films, Josephson junctions, and an interlayer insulating film. The same superconducting layer as the wiring is used for the superconducting film forming the Josephson junction electrode. The ground plane film is Nb film, the resistive film is Mo film, and the lower electrode film of Josephson junction is
The Nb film and upper electrode film were a Pb/In alloy film, and the interlayer insulating film was a SiO film. Once each integrated circuit is completed,
There is a wiring grid that intersects between the circuits, and this wiring grid is therefore the Nb film used for the Josephson junction lower electrode film. In order to match impedance, a ground plane film is also laid in the wiring area between circuits. The interlayer insulating film is a SiO film. Adjacent chains of multiplication circuits were connected in series to form a chain circuit of 40 stages on one wafer, and this was done in the following manner. As shown in FIG. 1, a rectangular window 1 is opened in the interlayer insulating film at the intersection of the wiring lines. Part of each wire 2 and 3 is inserted into the window, but it is kept within a range where it does not touch each other.
Next, a resist film pattern forming step and
Through a Pb/In film formation process and a lift-off process, a connection film 4 between wirings as shown in the figure is formed. Through these steps, as shown in FIG.
and was completed by using wiring connection 6.
In the figure, an input signal is input through a wiring 7, and an output signal is taken out through a wiring 8.
なおこの回路間接続においては不要であつた
が、直交する配線列において、それぞれの配線が
直線状に結線され、これらの配線が絶縁される必
要のある場合が生じる。このような結線は次のよ
うにして行なつた。第３図に示すように、層間絶
縁膜の下側配線３をPb・In合金超電導膜９によ
つて接続する。膜パターンの形成はリフトオフ法
によつて行なつた。次にPb・In超電導膜９をSiO
絶縁膜１０で覆う。絶縁膜パターンの形成もやは
りリフトオフ法により行なつた。次にやはり
Pb・In合金膜１１により上側超電導膜２の接続
を行なつた。この超電導膜パターンの形成もやは
りリフトオフ法により行なつた。 Although this connection between circuits was not necessary, there may be cases where each wire in orthogonal wire rows is connected in a straight line and these wires need to be insulated. Such connections were made as follows. As shown in FIG. 3, the lower wiring 3 of the interlayer insulating film is connected by a Pb.In alloy superconducting film 9. The film pattern was formed by a lift-off method. Next, the Pb/In superconducting film 9 is replaced with SiO
Cover with an insulating film 10. The insulating film pattern was also formed by the lift-off method. Next again
The upper superconducting film 2 was connected to the Pb/In alloy film 11. The formation of this superconducting film pattern was also carried out by the lift-off method.
以上説明したごとく、本発明においては、１枚
のウエハ上に多数個の回路を配列し、これら回路
間の配線および結線する方法を与えるものである
が、このような方法によつて次のような効果が生
まれる。
As explained above, the present invention provides a method for arranging a large number of circuits on one wafer and wiring and connecting these circuits. effect is created.
(1) チツプ片の製作、チツプキヤリアの製作およ
び、チツプのチツプキヤリア上へのマウントと
いう工程を不要とするので、回路系全体として
の工程を短縮できる。(1) Since the steps of manufacturing a chip piece, manufacturing a chip carrier, and mounting the chip on the chip carrier are not necessary, the steps for the entire circuit system can be shortened.
(2) １枚のウエハ上ですべての配線を行なうので
配線、および結線の欠陥を低減できる。(2) Since all wiring is done on one wafer, defects in wiring and connections can be reduced.
(3) 結線部をエチツングにより除去し、必要な結
線用マスクを用いることにより、結線の変更を
可能にする。(3) It is possible to change the wiring by removing the wiring by etching and using the necessary wiring mask.
(4) 記憶回路や演算回路など、品種の異なる回路
を同一ウエハ上に形成することにより、まとま
つた機能を有する計算回路を構成できる。(4) By forming different types of circuits, such as memory circuits and arithmetic circuits, on the same wafer, a calculation circuit with integrated functions can be constructed.
(5) 超電導薄膜の磁気遮蔽効果によつて、磁場信
号が別の配線に伝わる（クロストーク）を抑え
ることが出来る。(5) The magnetic shielding effect of superconducting thin films can suppress the transmission of magnetic field signals to other wiring (crosstalk).
第１図は回路間配線における結線部分を示す平
面図、第２図は回路４個を互に接続した全体図、
第３図は回路間配線における互に直交する結線部
分を示す平面図である。
１……窓、２，３……配線、４……接続膜、５
……直結型鎖状回路、９……超電導膜、１０……
絶縁膜。
Figure 1 is a plan view showing the connection part in the wiring between circuits, Figure 2 is an overall diagram showing how four circuits are interconnected,
FIG. 3 is a plan view showing mutually orthogonal connection portions in the inter-circuit wiring. 1... Window, 2, 3... Wiring, 4... Connection film, 5
... Directly connected chain circuit, 9 ... Superconducting film, 10 ...
Insulating film.
Claims (1)
線がリフトオフ法によつて形成された窓の内部で
交叉するように接続する結線方法において、(1)上
記超電導材料の配線の交叉部分の下側配線をリフ
トオフ法を用いてPbを主成分とする第１合金膜
で形成し、次に(2)上記第１の合金膜上に絶縁膜を
リフトオフ法により形成し、さらに(3)上記絶縁膜
上に上記下側配線と交叉するように上側配線をリ
フトオフ法を用いてPbを主成分とする第２の合
金膜で形成する、ことを特徴とする超電導回路の
結線方法。1. In a wiring connection method in which a plurality of superconducting material wirings formed on the same substrate are connected so as to intersect inside a window formed by a lift-off method, (1) below the crossing portion of the superconducting material wirings; The wiring is formed using a first alloy film containing Pb as a main component using a lift-off method, and then (2) an insulating film is formed on the first alloy film using a lift-off method, and (3) the above-mentioned insulating film is formed using a lift-off method. A method for connecting a superconducting circuit, characterized in that an upper wiring is formed using a lift-off method using a second alloy film containing Pb as a main component so as to intersect with the lower wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15527784A JPS6135578A (en) | 1984-07-27 | 1984-07-27 | Connection of superconductive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15527784A JPS6135578A (en) | 1984-07-27 | 1984-07-27 | Connection of superconductive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6135578A JPS6135578A (en) | 1986-02-20 |
| JPH0428154B2 true JPH0428154B2 (en) | 1992-05-13 |
Family
ID=15602380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15527784A Granted JPS6135578A (en) | 1984-07-27 | 1984-07-27 | Connection of superconductive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6135578A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818950A (en) * | 1981-07-28 | 1983-02-03 | Nec Corp | Multilayer wiring substrate |
| JPS5819742A (en) * | 1981-07-24 | 1983-02-04 | Pioneer Video Corp | Optical system driver for recorded information reader |
-
1984
- 1984-07-27 JP JP15527784A patent/JPS6135578A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5819742A (en) * | 1981-07-24 | 1983-02-04 | Pioneer Video Corp | Optical system driver for recorded information reader |
| JPS5818950A (en) * | 1981-07-28 | 1983-02-03 | Nec Corp | Multilayer wiring substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6135578A (en) | 1986-02-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |