JPS58187149U - 半導体素子用パツケ−ジ - Google Patents
半導体素子用パツケ−ジInfo
- Publication number
- JPS58187149U JPS58187149U JP1982085735U JP8573582U JPS58187149U JP S58187149 U JPS58187149 U JP S58187149U JP 1982085735 U JP1982085735 U JP 1982085735U JP 8573582 U JP8573582 U JP 8573582U JP S58187149 U JPS58187149 U JP S58187149U
- Authority
- JP
- Japan
- Prior art keywords
- package
- frame
- semiconductor devices
- curvature
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は従来の半導体素子用パッケージを示す平面図、
第2図は従来技術の欠点を説明する断面図、第3図は従
来の半導体素子用パッケージの溶接用フレーム周辺を示
す平面図、第4図は本考案の実施例による半導体素子用
パッケージの溶接用フレーム周辺を示す平面図である工 商、図において、1・・・溶接用フレーム、2・・・パ
ッケージ部材、3・・・半導体素子、4・・・ボンディ
ングワイヤ、5・・・パッケージ内部電極、6・・・素
子載置部、7・・・半導体素子の電極、8・・・ボンデ
ィングツールである。
第2図は従来技術の欠点を説明する断面図、第3図は従
来の半導体素子用パッケージの溶接用フレーム周辺を示
す平面図、第4図は本考案の実施例による半導体素子用
パッケージの溶接用フレーム周辺を示す平面図である工 商、図において、1・・・溶接用フレーム、2・・・パ
ッケージ部材、3・・・半導体素子、4・・・ボンディ
ングワイヤ、5・・・パッケージ内部電極、6・・・素
子載置部、7・・・半導体素子の電極、8・・・ボンデ
ィングツールである。
Claims (2)
- (1)キャップを封止するための溶接用フレームを有す
る半導体素子用パツゲ゛−ジにおいて、前記フレームの
平面形状が複数の曲率半径を有する” 曲線で構成
され、かつ、前記曲率半径はフレームの一辺の中央部よ
りフレームの一辺の端部において小さくなっていること
を特徴とする半導体素子用パッケージ。 - (2)前記フレームが2種類の曲率半径の曲線の組合せ
であることを特徴とする実用新案登録請求の範囲(1)
項記載の半導体素子用パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982085735U JPS58187149U (ja) | 1982-06-09 | 1982-06-09 | 半導体素子用パツケ−ジ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982085735U JPS58187149U (ja) | 1982-06-09 | 1982-06-09 | 半導体素子用パツケ−ジ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58187149U true JPS58187149U (ja) | 1983-12-12 |
JPS6234445Y2 JPS6234445Y2 (ja) | 1987-09-02 |
Family
ID=30094583
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982085735U Granted JPS58187149U (ja) | 1982-06-09 | 1982-06-09 | 半導体素子用パツケ−ジ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58187149U (ja) |
-
1982
- 1982-06-09 JP JP1982085735U patent/JPS58187149U/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6234445Y2 (ja) | 1987-09-02 |
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