JPS58182200A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS58182200A JPS58182200A JP57065677A JP6567782A JPS58182200A JP S58182200 A JPS58182200 A JP S58182200A JP 57065677 A JP57065677 A JP 57065677A JP 6567782 A JP6567782 A JP 6567782A JP S58182200 A JPS58182200 A JP S58182200A
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- signal
- refresh
- switching
- scan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
Abstract
Description
【発明の詳細な説明】
本発明はダイナミック型メモリ素子を用いた記憶装置に
関し、特に診断時において制御回路部のレジスタのスキ
ャンを行う主記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device using a dynamic memory element, and more particularly to a main memory device that scans registers in a control circuit section during diagnosis.
従来、記憶装置の制御回路において、フリップフロップ
を直列に！ｊ！綬したシフトレジスタにより故障箇所の
発見など管行うスキャン方式が多く用いられている。ま
た、ダイナミック型ＭＯ８ＩＣメモリ素子を使用した記
憶装置は、リフレッシエ動作管行なうに必要なりフレッ
シλ制御回路を備え１記憶情報を保持するためにリフレ
ッシュ動作全行なう必要がある。このためダイナミック
型メモリ素子を用いた場合のスキャン方式は、スキャン
動作実行時およびそれ以後も記憶的容管保証するために
、スキャン動作中もす７レツシ工動作【５Ｊ！行するも
のと、スキャン動作後は記憶内容を保証せずスキャン動
作中はりフレッシ、１実行しないものとがある。前者の
記憶装置の構成は、１８１図に示される。この図では、
全制御回路部のうちリフレッシュ制御回路を除く制御回
路部１の７リツプフロツプ５２１にスキャン動作制御信
号１２よシ論理的に直列接続しＡＮＤゲート５０．ＯＲ
ゲート５１およびフリップフロップ５２とからなるシフ
トレジスタを形成する。この回路にクロック信号１７ｔ
″与え、クロンク制御信号１８′ｆｒ論珊Ｉｌｌとする
と出力信号１４に各フリップフロップの論理状１Ｉｌ（
論理１−０」あるいは論理「ｌ」）が出力され、各７リ
ツプフロツノの論理状Ｉｌ！Ｉｆ知る事ができる。また
、入力信号１０に論理「０」もしくは「１」ｔクロック
信号１７に同期して与える事により、各フリップフロッ
プ５２に任意の論理状！ｌＡを与える事ができる。Conventionally, in the control circuit of a storage device, flip-flops were connected in series! j! A scan method is often used to detect failure points using a wired shift register. Furthermore, a storage device using a dynamic MO8IC memory element is required to perform a refresh operation control circuit, and is required to perform a refresh operation in order to retain one piece of stored information. For this reason, the scanning method when using a dynamic memory element requires seven retrieval operations [5J! In some cases, the memory contents are not guaranteed after the scan operation, and in some cases, the data is not executed during the scan operation. The configuration of the former storage device is shown in FIG. 181. In this diagram,
The scan operation control signal 12 is logically connected in series to the seven flip-flops 521 of the control circuit section 1 excluding the refresh control circuit out of all the control circuit sections, and an AND gate 50. OR
A shift register including a gate 51 and a flip-flop 52 is formed. This circuit has a clock signal of 17t.
'', and the clock control signal 18'fr logic Ill, the output signal 14 is the logic state 1Il(
Logic 1-0" or logic "l") is output, and the logic state Il! of each 7-lip float is output. If you can know. Furthermore, by applying a logic "0" or "1" to the input signal 10 in synchronization with the clock signal 17, each flip-flop 52 can be set to any logic state. It is possible to give lA.
一方、リフレッシュ制御回路２のフリップフロッグ５５
Ｈスキャン動作制御信号１２に無関係で、シフトレジス
タｔＳ成し危いため、この部分のフリップフロップの＃
ｌ理状態を知る事も、別の論理状層を与える事もできな
い欠点がある。On the other hand, the flip-flop 55 of the refresh control circuit 2
Since it is unrelated to the H scan operation control signal 12 and the shift register tS is in danger, the # of the flip-flop in this part is
It has the disadvantage that it cannot know the logical state or provide another logical layer.
また、スキャン動作中はり７レツンエをしない場合、１
８２図に示すように、スキャン動作制御信号１２により
リフレッシュ制御回路部２ｆ含む全制御回路部のフリッ
プフロップ５２．贋廖鍮理的に直列接続し、ＡＮＩ）ゲ
ート５０．５６．ＯＲゲート５１゜５７およびフリップ
フロップ５８からなるシフトレジスタを形成する。した
がって、全ツリツブフロップの論理状ａを知る事ができ
また任意の論理状態管与える−ができる。しかし、リフ
レッシュ制御回路２もスキャン動作管するため、リフレ
ッシ工動作が行われずｌピ憶内容が破壊されるので各７
リツグフロツプに論理値ケ与えて次の動作を再開しても
正しい記憶内容が読み出せない欠点がある。Also, if you do not perform 7 retsune during scanning operation, 1
As shown in FIG. 82, the scan operation control signal 12 causes the flip-flops 52 . ANI) gates 50.56. A shift register consisting of OR gates 51 and 57 and a flip-flop 58 is formed. Therefore, it is possible to know the logic state a of all tree flops, and to provide an arbitrary logic state. However, since the refresh control circuit 2 also performs a scan operation, the refresh operation is not performed and the contents of the memory are destroyed.
Even if a logic value is given to the logic flop and the next operation is restarted, the correct stored contents cannot be read out.
本発明の目的は、リフレッシＳ−動作管必要とする記憶
装置がスキャン動作を実施するときに、リフレッシュ制
御回路部を含めて全制御回路部のスキャン動作を行なう
場合と、リフレッシュ制御回路部はスキャンｗｈｈを行
わずリフレッシェ動作の制御？’！施し、他の制御回路
部のみスキャン動作全行なう場合とに切替ら１するよう
にすることにより、故障−ｌｆｒをが易にし九記憶装置
ｊｉを提供することにある。An object of the present invention is to perform a scan operation of all control circuit sections including the refresh control circuit section when a storage device requiring a refresh S-operation tube performs a scan operation; Control of refresh operation without performing whh? '! It is an object of the present invention to provide a nine-storage device ji in which failures -lfr can be made easier by switching from one to the other when only the other control circuit section performs the entire scanning operation.
本発明の構成は、ダイナミック型メモリ素子管用いた記
憶部上、この記憶部への入力信号により前記メモリ素子
のり７レツシ工動作全制御する鵠１の制御回路と、前記
記憶部の入出力信号の制御を行う第２の制御回路とを含
む記憶装置Ｋかいて、前記第１の制御回路のフリップフ
ロップケス中ヤン動作時とスキャンしない時に切替え、
かつこのスキャン動作時に前記ｉ＃！１およびＩ８２の
制御回路の各フリップフロップｆＷｊｌｌｌ的に直列接
続したシフトレジスタに切替える切替回路管備えること
を特徴とする。The configuration of the present invention includes a control circuit on a storage section using a dynamic memory element tube, which controls all resetting operations of the memory element 7 based on input signals to the storage section, and a control circuit for controlling the input/output signals of the storage section. a storage device K including a second control circuit for controlling the first control circuit; switching the first control circuit between a flip-flop operation and a non-scan operation;
And during this scan operation, the i#! The present invention is characterized in that it includes a switching circuit tube for switching to a shift register connected in series with each of the flip-flops fWjlll of the control circuits 1 and I82.
次に本発明について図面全参照して詳細に説明する。Next, the present invention will be explained in detail with reference to all the drawings.
第３図は本発明の実施例のブロック図である。FIG. 3 is a block diagram of an embodiment of the invention.
この実施例の記憶装置ｉは、リフレッシュ制御回路部２
、リフレッシュ制御回路を除く制御回路部１、ダイナミ
ック型メモリ素子で作られた記憶部３、スキャン動作時
においてリフレッシュ制御回路部２のスキャン動作管す
るものとしないものとに切替える切替回路部４から構成
される。The storage device i of this embodiment has a refresh control circuit section 2.
, a control circuit section 1 excluding the refresh control circuit, a storage section 3 made of a dynamic memory element, and a switching circuit section 4 that switches between controlling and not controlling the scan operation of the refresh control circuit section 2 during scan operation. be done.
通常時の読出し、書込み、リフレッシェ動作等のときに
は、クロック信号１７を与え１クロック制御部号１８を
論理「“ｌ」として、スキャン動作制御信号１２を論理
「０」にする。このときはリフレッシュ制御回路部２と
リフレッシュ制御回路を除く制御回路部１との７リツプ
フロツプ５３．５８はシフトレジスタｆ構成せずに、中
央処理装置等の上位装置からの制御信号１１．１５によ
り論理処理。During normal read, write, refresh, etc. operations, the clock signal 17 is applied, the one-clock control unit 18 is set to logic "1", and the scan operation control signal 12 is set to logic "0". At this time, the seven flip-flops 53 and 58 of the refresh control circuit section 2 and the control circuit section 1 excluding the refresh control circuit do not constitute a shift register f, but are logically controlled by control signals 11 and 15 from a host device such as a central processing unit. process.
順序処理が行わｆ′１％記憶部３に対して信号１３．１
６會送り続出し、書込み、リフレッシュ等の動作を実施
する。The sequential processing is performed and the signal 13.1 is sent to the f′1% storage unit 3.
Operations such as continuous transmission, writing, and refreshing are performed for 6 sessions.
スキャン動作時においては、スキャン動作制御信号１２
が論ｆＭ ｒｌＪとなる。このときスキャン切替信号１
９が論理「１」であわば、切替回路部４で論理がとられ
、す７レツシ工制御回路部２およびリフレッシュ制御回
路を除く制御部１の７リツプフロツプ５３．５８はすべ
てシフトレジスタとして論理的に直列接続される。した
がって、クロック制御信号１８を論理「１」にし、クロ
ック信号１７を与えると出力１４にはりフレッシェ制御
回路部２およびリフレッシュ制御回路部を除く制御回路
部１の７リツプ７０ツブの論理状態が出力される。During scan operation, scan operation control signal 12
becomes the theory fM rlJ. At this time, scan switching signal 1
9 is a logic "1", so to speak, the logic is taken by the switching circuit section 4, and the 7 lip-flops 53 and 58 of the control section 1 except for the 7 reset control circuit section 2 and the refresh control circuit are all logically set as shift registers. connected in series. Therefore, when the clock control signal 18 is set to logic "1" and the clock signal 17 is applied, the logic states of 7 and 70 bits of the control circuit section 1 excluding the Freshé control circuit section 2 and the refresh control circuit section are outputted to the output 14. Ru.
−万、切替信号１９が論理「０」であればリフレッシュ
制御回路部２の７リツプ７０ツブ５８はシフトレ・〉ス
タケ構成せずに制御信号１５により論理処理、１頃序処
４ｆ−行ない記憶部３に制御信号１６を送りリフレッシ
ュ動作を実施する。この時リフレッシュ制御回路部２の
７リツプフロ、ノブには、クロック制御信号１８の論理
状態に無関係にクロック信号１７と同等り【コック信号
が与えられる。- 10,000, if the switching signal 19 is logic "0", the 7 lip 70 knob 58 of the refresh control circuit section 2 performs logic processing according to the control signal 15 without forming a shift lever. 3 to perform a refresh operation. At this time, a cock signal equivalent to the clock signal 17 is applied to the refresh control circuit section 2's 7-lip flow knob, regardless of the logic state of the clock control signal 18.
またリフレッシュ制御回路管除く制御回路１の７リノブ
フロノグはシフトレジスタとして直列接続される。クロ
ック制御信号１８が論理「１」となると、クロック信号
１７がリフレッシュ制御回路を除く制御回路部１のフリ
ップフロップに入力さね、出力信号１４にはりフレッシ
ェ制御回路ｔ−除く制御回路部ｌのフリップ７０ツグの
論理状態がｊ臓次出力される。Furthermore, the 7 Rinobronogs of the control circuit 1 excluding the refresh control circuit tube are connected in series as a shift register. When the clock control signal 18 becomes logic "1", the clock signal 17 is input to the flip-flop of the control circuit section 1 excluding the refresh control circuit, and the output signal 14 is input to the flip-flop of the control circuit section 1 excluding the refresh control circuit t--the flip-flop of the control circuit section l excluding the refresh control circuit. 70 logical states are outputted every time.
本発明は、以上説明した様に、リフレッシュ制御回路部
とリフレッシュ制御回路を除く制御部と記憶部とリフレ
ッシュ制御回路のスキャン切替回路部とから構成するこ
とにより、スキャン動作時［＋７フレソシユ制御回路を
含めて５Ａ瑚する場合とりフンノ／ユ制御回路部を除い
て実施する場合とに切替らねるので、故障診断時に論理
状態の点検および試験信号の供給が容易に出来、ｔた故
障診断時の余計な中断をなくすこともできる。As explained above, the present invention includes a refresh control circuit section, a control section excluding the refresh control circuit, a storage section, and a scan switching circuit section of the refresh control circuit, so that the Since there is no switching between the case of using 5A including the control circuit and the case of excluding the control circuit section, it is easy to check the logic state and supply test signals during fault diagnosis, and there is no need to worry about unnecessary trouble during fault diagnosis. It also eliminates interruptions.
第１図、Ｗ＆２図は従来のスキャン動作可能な記憶装置
の実施例を示すブロック図、＄３図は本発明の一実施例
を示すブロック図である。
１・・・・・・リフレッシュ制御回路部、２・・・・・
・リフレッシュ制御回路管除く制御回路部、３・・・・
・・記憶部、４・・・・・・切替回路部、１０・・・・
・・スキャン動作時の入力信号、１１・・・・・・他装
置と記憶装置間のリフレッシュ関係を除く信号、１２・
・・・・・スキャン動作制御信号、１３・・・・・・リ
フレッシュ関係を除く記憶部への入出力信号、１４・・
・・・・スキャン動作時の出力信号、１５・・・・・・
他装置と記憶装置間のりフレッシ纂関係信号、１６・・
・・・・記憶部へのりフレッシェ関係信号、１７・・・
・・・クロック信号、１８・・・・・・クロック制御信
号、１９・・・・・・スキャン動作切替信号、５０゜５
４１５６．６１，６５，６７．６８・・・・・・ＡＮＤ
ゲート。
５１．５７．６９・・・・・・ＯＲゲート、５２．５５
・・・・・・７リノプ７０ノグ、５３．６２，６３．６
６・・・・・・インバータ。
６４・・・・・・ＮＡＮＤゲート である。
ｒ
９り、 ７ し１
１σ
η ／（２１FIGS. 1 and 2 are block diagrams showing an embodiment of a conventional storage device capable of scan operation, and FIG. 3 is a block diagram showing an embodiment of the present invention. 1... Refresh control circuit section, 2...
・Control circuit section excluding refresh control circuit tube, 3...
...Storage section, 4...Switching circuit section, 10...
...Input signal during scan operation, 11... Signal excluding refresh relationship between other devices and storage device, 12.
...Scan operation control signal, 13...Input/output signal to the storage unit except for refresh-related signals, 14...
...Output signal during scan operation, 15...
Fresh compilation related signal between other devices and storage device, 16...
...Freche related signal to storage section, 17...
... Clock signal, 18 ... Clock control signal, 19 ... Scan operation switching signal, 50°5
4156.61, 65, 67.68...AND
Gate. 51.57.69...OR gate, 52.55
...7 linop 70 nog, 53.62, 63.6
6...Inverter. 64...NAND gate. r 9ri, 7 shi1 1σ η /(21
Claims (1)
部への入力信号により前記メモリ素子のり７レツシ工動
作ｔｆｌｌＪ御する第１の制御回路と、前記記憶部の入
出力信号の制御管行うＩｉ２の制御回路とを含む記憶装
置において、前記＠１の制御回路の７リツプフロツプを
スキャン動作時とスキャンしない時に切替え、かつこの
スキャン動作時に前記Ｗ４１およびＩ！２の制御回路の
各フリッグ７０ッグｔ−，＊埋的に直列Ｗ！続したシフ
トレジスタに切替える切替回路を備えることを特徴とす
る記憶装置。A storage unit using a dynamic memory element tube, a first control circuit that controls the resetting operation of the memory element 7 according to an input signal to the storage unit, and a control circuit Ii2 that controls input and output signals of the storage unit. 7 lip-flops of the @1 control circuit are switched between scan operation and non-scan operation, and during the scan operation, the W41 and I! circuits are switched. Each flip 70gt- of the control circuit of 2,* buried in series W! 1. A storage device comprising a switching circuit for switching to a continuous shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065677A JPS58182200A (en) | 1982-04-20 | 1982-04-20 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065677A JPS58182200A (en) | 1982-04-20 | 1982-04-20 | Storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58182200A true JPS58182200A (en) | 1983-10-25 |
| JPS6349811B2 JPS6349811B2 (en) | 1988-10-05 |
Family
ID=13293867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57065677A Granted JPS58182200A (en) | 1982-04-20 | 1982-04-20 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182200A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6446293A (en) * | 1987-04-16 | 1989-02-20 | Tandem Computers Inc | Scanning tester for digital system with dynamic random access memory |
| JPH04288648A (en) * | 1990-07-03 | 1992-10-13 | Digital Equip Corp <Dec> | Mode changeover of memory device by diagnostic scan |
| JP2008089545A (en) * | 2006-10-05 | 2008-04-17 | Matsushita Electric Ind Co Ltd | Analyzer |
-
1982
- 1982-04-20 JP JP57065677A patent/JPS58182200A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6446293A (en) * | 1987-04-16 | 1989-02-20 | Tandem Computers Inc | Scanning tester for digital system with dynamic random access memory |
| JPH04288648A (en) * | 1990-07-03 | 1992-10-13 | Digital Equip Corp <Dec> | Mode changeover of memory device by diagnostic scan |
| JP2008089545A (en) * | 2006-10-05 | 2008-04-17 | Matsushita Electric Ind Co Ltd | Analyzer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6349811B2 (en) | 1988-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2614345B2 (en) | Scan flip-flop | |
| JPH0465350B2 (en) | ||
| JPS61204744A (en) | Memory array built-in type logical lsi | |
| JPH01195379A (en) | Logic circuit | |
| JPS58182200A (en) | Storage device | |
| JP3612190B2 (en) | Various kinds of test mode setting method using external pins, circuit thereof, and apparatus having the circuit | |
| JPS63148179A (en) | Scan-path circuit | |
| JPS6325749A (en) | Semiconductor storage element | |
| JPS6150340B2 (en) | ||
| JP2877505B2 (en) | LSI mounting board and data processing device | |
| KR100345673B1 (en) | integrated circuit capable of self-testing | |
| JP2505571B2 (en) | Storage device diagnostic method | |
| JPS59746A (en) | Diagnostic system of logical circuit | |
| JPS61260172A (en) | Logic circuit | |
| JPS59173848A (en) | Tracing system | |
| JPH0320710B2 (en) | ||
| JPH02144642A (en) | Test circuit for memory | |
| JPS61256268A (en) | Testing apparatus | |
| JPS6118785B2 (en) | ||
| JPH02191045A (en) | Microprogram controller | |
| JPS5890253A (en) | Working history storage device | |
| JPS62165162A (en) | Test circuit for logic circuit | |
| JPS59200354A (en) | Debug system | |
| JPH01153986A (en) | Test signal generating circuit | |
| JPH03227033A (en) | Logical circuit |