JPS59200354A - Debug system - Google Patents

Abstract

PURPOSE:To reproduce simply and quickly an optional state by storing the scan- out information to an external memory part for each clock by a single clock mode when an information processor is tested. CONSTITUTION:A scan-out instructing signal is sent to a scan-in/scan-out control circuit 11 from a CPU 1. An address is sent back to the CPU 1 from the circuit 11, and the scan-out information is stored in a scan-out memory 3 in accordance with said address. Then the contents of the scan-out information are stored in an external memory part 5 via a test processor 4. Then an optional state preceding the present state can be reproduced even when the contents of the part 5 are read out by designating an address by the scan-out instructing signal in a single clock mode.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention provides a single clock mode for testing an information processing device having a scan-in/scan-out check function for a processing circuit and a scan-out memory. It relates to a debugging method that allows reproducing any previous state.

(2) Conventional technology and problems Conventionally, it is scanned into an information processing unit (CPU).

It has a scan-out function to check the processing circuit and a scan-out memory, and if an error occurs in the processing information, the scan-out information is memorized, and the data is stored in an external storage unit so that it can be reproduced when necessary. The following debugging method is used. FIG. 1 shows one example, and FIG. 2 shows the operating procedure. As shown in FIG. 1, a scan-out memory 6 is provided in the system control interface 2 controlled by the CPU 1, and when an error occurs in the processing information of the circuit controlled by the CPU 1, this error is recorded. In order to keep the CPU
The CPU 1 sends an error record request command to the system control interface 2 and performs a scan error, and the CPU 1 sends a machine check request command to the system control interface 2, and the contents of the scan out memory 3 are set to 5VP.
4 and stored in the external storage unit 5.

In order to reproduce the contents of this external storage section 5, a predetermined address must be read from the external storage section 5 for each requested command during the free time of cPUl, but if you want to refer to part of the contents, However, the problem is that the address must be reproduced from the beginning for each instruction, which takes time. Therefore, it is inconvenient to immediately refer to any previous state rather than the current state.

(3) Purpose of the Invention The eye collar of the present invention is capable of scan-in to an internal processing circuit.
To provide a debugging method capable of displaying any previous state from the current state in a single clock mode when testing an information processing device having a scan-out check function and a scan-out memory.

(4) Structure of the Invention In order to achieve the above object, the debugging method of the present invention scans in and clocks the processing circuit.

An information processing apparatus having a control means for performing a check by scanout and a scanout memory, comprising means for storing system scanout information in the scanout memory in a single clock mode, and a means for storing the contents of the scanout memory in a test processor. When testing the processing device, scanout information for each lock can be stored in the external storage unit in single clock mode, and can be used for testing when necessary. This system is characterized in that the state in the external storage section is scanned in via the processor, and any previous state can be reproduced from the current state.

(5) Examples of the invention FIG. 6 is an explanatory diagram of the configuration of the embodiment of the present invention.

In the figure, a scan-out instruction signal is sent from the CPU 1,
In other words, the output of the logical product with the operating status register (OPSR) that makes it valid in single clock mode is sent to the scan-in/scan-out control circuit 11, and the address is sent to the CPUI through the entire scan-in/scan-out address bus. Then, the scan-out information is stored in the scan-out memory 6 according to the address, and after the storage is completed, the machine check information is stored in the 70-pin disk of the external storage unit 5 through the 5VP 4 as shown in FIG.

When reading the contents of the floppy disk in the external storage unit 5, the current state and any previous state can be reproduced by specifying the address at the same time as the 7 clock mode using the scan-out instruction signal. It has been made possible.

In this case, especially in the present invention, in the single clock mode, the operating state register (OPSR) that makes this valid is incremented by the address count value. Therefore, since it is possible to return to and reproduce the count value already stored in the external storage unit 5, fine-grained reference is performed each time by specifying the address count value.

FIG. 4 is a detailed explanatory diagram of the main parts of the embodiment shown in FIG. 6.

In the same figure, a flip-flop (F
F) 61” when a single clock is given to 21.

@0'' is generated alternately, and the state setting of 1'' 11011 is performed in the ratte 22 at an arbitrary clock.

On the other hand, an address count value is set in the operating state register (OPSR) 25, and this count value enables two-way output during single clock, and the output of the AND circuit 24 is used as a scan-out instruction signal to control scan-in and scan-out. The AND circuit 26 which is sent to the circuit 11 and sets the FF 25 and is provided before the scan-out memory 6
One of the inputs is turned on, and the scan-out information based on the error record request output from the error record circuit 27 is stored in the scan-out memory 6 by the command of the CPU 1. Upon completion of this scan-out information, the second record circuit 27 and the FF 25 are reset. AN included in 5VP4 before this FF25 reset
By turning on the D circuit 31, the FF62 is set, and one input of the AND circuit 62 provided in front of the external storage section 5 is turned on, and the machine check record circuit 36 is controlled by the 5VP4. The information based on the machine check record request that is output blank is stored in the external storage unit 5. Upon completion of this storage, the machine check record circuit 63 and F'F 32 are reset and the storage procedure is completed.

Next, when reading out the self-answer stored in the external self-memory section 5, it can be read out using the address count value as a key, so there is no need to return the answer for each command as in the conventional case.

(6) According to the present invention, when testing an information processing device having a scan-in/scan-out check function for an internal processing circuit and a scan-out memory, the single clock mode can be used. By storing the scanout information for each lock in the external storage unit, it is possible to read out and reproduce the address count value as a key or - when necessary. The state can be reproduced immediately.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of the conventional example, Fig. 2 is an explanatory diagram of the operation of the conventional example, Fig. 6 is an explanatory diagram of the configuration of the embodiment of the present invention, and Fig. 4 is a detailed diagram of the main part of the embodiment of the present invention. This is an explanatory diagram. In the figure, 1 is an f'# information processing device, 3 is a scan-out memory, 4 is a test processor, and 5 is an external device. section storage section. Patent applicant Fujitsu Ltd. sub-agent Patent attorney 1) Yoshishige Saka

Claims (1)

[Claims] Scan-in and clock increment for the processing circuit. In an information processing apparatus having a control means for performing a check by scan-out and a scan-out memory, means for storing system scan-out information in the scan-out memory in a single clock mode, and storing the contents of the scan-out memory in a test processor? The system is provided with means for storing data in an external storage section via a memory card, and stores scan data for each valley lock in the external storage section in a single clock mode during testing of the processing device. A debugging method characterized in that the state in an external storage unit is scanned in via a test processor when necessary, and any state before the current state can be reproduced.