JPS59173848A - Tracing system - Google Patents

Abstract

PURPOSE:To utilize a trace memory effectively and to facilitate analysis of data by providing an event waiting loop judging section in a tracing device and writing only data of the first time and last time in a trace memory. CONSTITUTION:A reading command signal of a status register 20 of an input/ output controlling device 53 and a signal that indicates bit information of busy flag that indicate the state of event waiting or not of the status register 20 are inputted to an event waiting loop judging section 18. Output of the event waiting loop judging section 18 is inputted to AND gates 15-17, and only data that are related to the first and last event waiting loops are written in trace memories 9, 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a tracing method, and more specifically, to a program execution tracing method for the purpose of program debugging, failure analysis, operation monitoring, etc. in a computer or the like.

[Prior art and its problems]

Conventionally, a method of tracing execution data addresses has been widely used for tracing the execution of this type of program.

In FIG. 1, 51 is an arithmetic processing unit, 52 is a main storage device, 56 is an input/output control device, 55 is a trace device, 1 is a common bus connecting the above devices, 56 is a trace data display device, and 57 is a trace data display device. It is an information input device.

FIG. 2 is a block diagram of a conventional example of the data collection circuit of the tracing device 55 of FIG. In the figure, 1 indicates a common bus corresponding to 1 in FIG. 1, and 2, 3, and 4 indicate a control signal group, an address signal group, and a data signal group on the common bus 1, respectively. Note that 6 is an address signal group latch register, 7p is a data signal group latch register, 5 is a timing jig control unit, 8 is a trace memory address counter, and its output 11 becomes the address input for trace memories 9 and 1o. , 12.13 are write enable signals for trace memories 9 and 10, respectively.

The execution data (address signal and data signal) taken in from the common bus 1 is passed through the latch register 6°7.
Each time a program instruction is executed, the trace memory address counter 8 is incremented, and the data is sequentially stored in the trace memories 9 and 10.

If we trace the execution data of a program that has some kind of event waiting loop as shown in Figure 3 using the conventional method, the contents written to the trace memories 9 and 10 will be written in the order of execution of the program as shown in Figure 3. As shown in Figure 4, until the event or loop stops when an event occurs,
All data that appears repeatedly will be written.

More specifically, FIG. 6 illustrates a flowchart of a loop portion of a program having an event waiting loop. In the figure, α is a read command (RD-5TR) for the status register of the input/output control device, etc.
Step b is EUSI!, which indicates whether or not the read status register is waiting for an event. : Test instruction (TBi
T BUSY), C depends on the result of execution of the flag test instruction in step b, BUS
If the Y flag is 11", jump to address A and 10"
This is the execution step of a conditional jump instruction that does not jump. As can be easily seen from the figure, when the EUSY flag is 11'', it jumps to address A and enters the event waiting loop, and when the EUSY flag is 10'', the event for which it was waiting has occurred. Proceed in the direction of E, which creates a loop, and the loop will disappear.

FIG. 4 shows the state written to the trace memory 1o at this time. When one loop occurs, the status register read command (RD5) is executed as shown in the figure.
TR), BUSY 7 Ragno Test Instruction (TEiT
RUBY) and conditional jump instruction to address A (BPA
) is viewed and written n times.

In general, tracing such a loop step once is sufficient for debugging the program, analyzing failures, monitoring the operation, etc. described above.9 Although tracing such a loop step multiple times is not necessary, Therefore, it is unnecessary to trace a loop step multiple times, generally a very large number of times, and the effective utilization rate of the trace memory is extremely reduced.

Also, tracing a loop step multiple times (typically a very large number of times) can occupy a large portion of the trace memory and may prevent you from writing the data you need to the trace memory. The disadvantage is that you have to retrace the trace several times until you can trace it.

Furthermore, when analyzing traced data in which a loop step is traced multiple times (many times), the necessary data must be searched for from a large amount of data, which is time-consuming.

[Purpose of the invention]

The present invention eliminates the above-mentioned disadvantages and shortcomings of the above-mentioned prior art tracing schemes, enables efficient use of trace memory in tracing loop steps, and 2.
It is an object of the present invention to provide an efficient tracing method that improves operability, simplifies the task of searching for necessary data from a trace memory, and facilitates data analysis.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a block diagram of an embodiment of the present invention. In FIG. 5, reference numerals are the same as those shown in FIGS. 1 and 4. In addition, 15.16.1 in the figure
7 is an AND gate, 18 is an event waiting loose judgment unit,
23 is a control signal called 'I'LOCK signal; 2
4 indicates an inverter, and 20 of the input/output control device 53
is a status register, 21 is a read instruction signal of status register 2o, and 22 is a status register ST.
The EUSY flag (1 bit) in R is a signal indicating that 11'' is J+''.

6 is a diagram showing details of the connection configuration of the event waiting loop determining section 18 in FIG. 5, and FIG. 7 is an operation time chart of the event waiting loop determining section 18 in FIG. 6.

In FIG. 5, when the control signal, that is, the TLOCK signal 26 output from the event waiting loop determining unit 1B is 'o', the signal 'o# is negated by the inverter 24 and the signal #1
15. In order to make the AND gate 15.
It has exactly the same connection state as the trace device 55 shown in the figure, and operates in exactly the same way as the trace device 55° shown in FIG.

However, when the TLOCK signal 25 becomes 11#, 1o'', which is negated by the inverter 24, is input to one input terminal of the AND gates 15, 16.17, and the gates 15, 16.17 are turned off. To make it conductive,
Incrementing of trace memory address counter 8 and writing to trace memories 9 and 1o are stopped.

In this way, set the τLOCK signal 23 to 1o'' or 11''
By doing so, the trace memory 9. You can select the data to be stored at the same time.

In the input/output control device 53 in FIG. 5, the reading command signal 21 of the status register (STR) 20 is R.
It becomes valid ('1') when executing the D STR instruction (see Figures 3 and 4).The RUB Y signal 22 is set when one bit in the status register (STR) 20, that is, the EUSY flag, is '0'. 10 according to ``or 〆1''
``is 11''. In the program shown in FIG. 3, the loop steps are repeated until this EUSY signal 22 becomes 'o#.

FIG. 6 is a block diagram of an example of a connection configuration of the event waiting loop determining section 18 provided in the tracing device 55 of FIG. 5 according to the present invention.

In Figure 6, 30.35 is an inverter, 31, 32
゜33.36 is and gate, 34 is or goo, g, 37, 38 is 7 lip flop, 21, 22
．． 23 are the status register read instruction signal (STRR), the signal indicating the state of EUSY 7 lag (BUSY), and the AND gate 15.16.17.
This shows the TLOCK signal that controls the TLOCK signal.

In the input/output control device 56 of FIG. 5, the signal 22 (BUSY) indicates "0" if it is not in an event wait state.

In the event waiting loop determination unit 18 (FIG. 6), the input terminal 2
If *0'' is input to 2, the AND gate 31 is non-conductive and its output is 10'' regardless of the input 110Zg1'' of the input terminal 21 (unless it is in the event wait state). Therefore, the output of the AND gate 33 is "0", and the normal state τ is the flip Flora 7' 38 (F
Since F-2) is in the reset state, its output Q is 10''
Yes, the output of the OR gate 34 which uses the output 10'' of the AND gate 33 and #0'' of the output Q of the 7 lip-flop 38 is 10'', so the AND gate 36
The output signal 25 (TLOCK signal) is 10”,
As mentioned above, AND gates 15, 16, 17 are held conductive and trace memories 9, 10 are written.

When the event wait state is entered, the signal 22 (BUSY signal) in the input/output control device 53 of FIG. 5 becomes 11''.

In the event waiting loop determining section 18 (FIG. 6), 11'' is input to the input terminal 22 (EUSY).

At this time, in the input/output control device 53, the status
The register/read command signal is not issued, that is, the input terminal 21 of the event waiting loop determining section 18 (FIG. 6)
It is assumed that the signal "IIO" continues to be input to.

FIG. 7 is an operation time chart of the event waiting loop determination unit 18 in FIG.
1 = (STRR signal) and signal 22 (BUSY' signal) shift flip-flop 67 (FF-1), 38
It is a figure which shows the state of (FF-2) and the situation where a TLOCK signal changes.

In FIG. 7, at time t□, it is necessary to wait for an event, and while signal 21 (5TRR signal) remains '0', signal 22 (EUSY signal) changes from 10'' to #1'. do. Then, in the AND gate 62, #1" which is negated by the inverter 50 of IIO" of the signal 22 is inputted to one input terminal, but since "to" of the signal 21 is inputted to the other input terminal. , its output is still 10". In this case as well, the output of the OR gate 34 is '0' as in the case when the signal 22 (BUSY) is '0' before time t1, so the signal 25 (TLOC
K signal) is #0''.

Suppose that in this state, the status register read command signal is issued and the signal 21 remains at g1 for a certain period of time.In FIG. 6, as shown at time t in FIG.
(5TRR signal) becomes 1″ for a certain period of time. Therefore,
The output of the AND gate 31 is #1'', and the output of the flip-flop 37 (FF-1) is 1.
1" is input, and the output of AND gate 32 is 0".
is also input to the reset terminal R.

At some point during the period when the signal 21 (STRR signal) is at '1', lock is applied and the slip-flop 37 (FF
-1) is set, and its output Q becomes met.

At time t, the AND gate 33 outputs 11" for both of the two inputs, but at time t4
When signal 21 (5TRR signal) becomes 10',
When the output of AND gate 61 becomes 10'', one input of AND gate 61 becomes 10'', so one input of 33. becomes 1.
It will now output 0'. Time t, and 1. For a short period of time, the outputs of the AND gate 33 and the OR gate 34 are not ``1'', and therefore the output of the AND gate 3b, that is, the signal 23 (TLOCK signal) is ``1'', but for a short period of time. Since this is the time, there is no effect on the write operation to the trace memos IJ9 and IJ10. Note that the fact that the signal 23 (TLOCK signal) becomes 1'' between time points 'fi+'4 can be prevented by making a slight change in the circuit structure, such as inserting a delay circuit, if necessary.

Thus, during the first wait loop (see FIG. 4), the signal 23 ('rLOcK signal) is 10'' and is written into the trace memories 9, 10.

At the beginning of the second waiting loop, i.e. at the seventh
Assume that the signal 21 (STRR) becomes '1' again at time t in the figure. Then, the AND gate 3
1 output is 11'', flip-flop 37 (F
F-1) is in the set state and its output Q is "1", and the AND gate 33 outputs '1' because the above two outputs '1' are input.

This output camera 1'' inputs the OR gate 54 to the AND gate 3, and therefore the output of the AND gate 5 is 1.
1", signal 23 (TLOCK signal) becomes 11", that is, at time t, trace memo IJ9,1
Praise for 0 is prohibited.

The output "1" of the above AND gate 33 also reaches the set input terminal S of the flip-flop 5B (FF-2), while its reset input terminal R is connected to the AND gate 62.
Since the output '0'' is input, the slip-flop 38 is set when it receives the clock at time t6,
Its output Q is 11".

At this time, after the signal 21 (5TRR signal) returns to 0'', the signal 23 (TLO'CK No. 7) is held at '1' by the output Q of the flip-flop 38 at '1'.

In this way, writing to the trace memory 9.10 is prohibited for the second and subsequent waiting loops.

In this state, that is, the flip-flop 37 (FF-
1) and 38 (77F-2) are set,
And while the signal 22 is gO'', the signal 21 (STRR
Signal 23 (TLOC
In other words, the data of the first event waiting loop is stored in the trace memories 9 and 10.
After writing into the loop, data will not be written in the second and subsequent loops as long as the above state continues.

° Now, due to changes in the state, there is no need to wait for an event.
When the process is ready to proceed, the RUBγ flag 4 becomes 10'' and the υ signal 22 becomes 10''.

Time point 1 in Figure 7. Suppose that this state is reached.

It is assumed that thereafter, at time t, a status register read command signal is issued and the signal 21 (5TRR signal) becomes 1.

Since the signal 21 is '1' and the signal 22 is '0', the output of the AND gate 31 is '0', followed by the AND gate 63.
The output of the OR gate 54 is 10'', and the output of the OR gate 54 is the # of the output Q of the flip 70 tube 38 (FF-2).
11'' to pass 1'', which becomes one input of AND gate 66.

Also, the output of the AND gate 62 is ``1'' because 11'' of the signal 21 is input to one of its input terminals, and ``1'' which is negated by the inverter 60 of the 10' of the signal 22 is input to the other input terminal. This output camera 1" is input to the inverter 65 through the line 69, and is negated and becomes '0", which is AND.
input to gate 36;

Therefore, the AND gate 66 outputs 10'', which is the signal 23 (TLOCK signal)
15, 16, and 17, their gates become conductive, and writing to the trace memories IJ9 and IJ10 begins.

If this event waiting loop ends, the loop ends (E) without jumping to address A when step C in FIG. 6 is completed.

Therefore, in the above data of the event waiting loop, the first and last (nth) data are traced.
Memo I) Data written in 9.10 and intermediate loops are not written.

In FIG. 7, the signal 21 (STRR
While the signal) is still z1'', flip 70 knob 37
Since '0' is input to the set input terminal S of (FF-1) and 38 (FF-2), and '12' is input to each of the reset input terminal R, the signal 21 (STR,
At time t during the period when the R signal) is still '1', the seven lip-flop 37.3B is clocked and reset.

When the signal 21 (STRR signal) returns to 10'', the output of the AND gate 32 (signal on line 39) also returns to #0'', and the event waiting loop determining section 18 enters the normal state.

Then, it outputs 10'' as a signal 25 (TLO (l signal)).

FIG. 8 shows the result of writing data related to the event waiting loop to the trace memory as described above.
Following the first loop of the PA steps, the last loop (nth loop) is traced to memory 1 without any pause.
This indicates that it has been written to 0.

The configuration of the event waiting loop determination unit 18 is not limited to that shown in FIG. 6, and various modifications are possible.

〔Effect of the invention〕

According to the present invention, an event waiting loop determination section is provided in a tracing device connected to a common bus of a computer, and a program having an event waiting loop as shown in FIG. 3 is traced before and after the event waiting loop. In this case, the read instruction signal of the status register of the device subject to the event and the signal indicating the state of the event are input to the event waiting loop determination unit, and only data regarding the first and last event waiting loop is input. is now written to the trace memory.

Therefore, it is avoided that the trace memory is filled with only the data of the step of the event waiting loop, making it impossible to trace other necessary data, and this has the effect of improving the effective use and utilization efficiency of the trace memory. . As for the event waiting loop, since the first and last data are written to the trace memory, sufficient data can be obtained and the process of searching for the necessary data when tracing later is simplified. This has the effect of improving operability.

Furthermore, in order to trace the first and final times of the event waiting loop, a special program is used to perform special processing (starting and stopping of the trace operation is controlled by instructions from the processing unit, and the event waiting state is In this case, there is no need to perform processing such as prohibiting tracing, and the effect is that it can be done by simply adding hardware.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of a general computer system equipped with a trace device according to the prior art, Fig. 2 is a block diagram of an example of a trace device according to the prior art, and Fig. 3 is an example of an event waiting loop program. 4 is a diagram showing the state of the trace memory in which data of the event waiting loop is written according to the prior art. FIG. 5 is a block configuration diagram of an embodiment of the present invention. The figure is a diagram showing an example of the circuit configuration of the event loop determining section provided in the embodiment of FIG. 5 according to the present invention, and FIG. FIG. 8 is a diagram showing the state of the trace memory into which data of the event waiting loop is written according to the present invention. 51... Arithmetic processing unit, 52... Main storage device, 5
6... Input/output control device, 55... Trace device,
1... Common bus, 5... Timing control circuit, 6.
...Address signal group latch register, 7...Data signal group latch register, 8...Tray number/memory...
Address counter, 9,10...Trace memory, 15,16,17゜20...Status register, 7,3B...Flip-flop Patent applicant Fuji Electric Manufacturing Co., Ltd. (1 other person) Representative Patent Attorney Gobe Tamamushi (3 others) JP-A-59-173848 (6) Figure 1 Figure 4 Figure 3 Figure 2 Figure 6 Welcome - Figure 7 FIQ FF:? Q TLOC scale L □ Fig. 8

Claims (1)

[Claims] In a computer system that includes an arithmetic processing unit, a main memory unit, and an input/output control unit, and is configured by connecting multiple of the above devices to a common bus, program execution data and addresses are transferred from the common bus to the trace memory. The trace device stores a read instruction signal of the status register of the input/output control device and bit information of a busy flag in the status register indicating whether or not to wait for an event. The event waiting loop determining section has an event waiting loop determining section which inputs a signal shown in FIG. and the data of the last loop when the busy bit indicating the event waiting state changes to the state indicating not waiting for an event are stored in the trace memory.