JP3040599B2 - Automatic generation of instruction sequence for pipeline operation verification - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of automatically generating an instruction sequence for logic verification of a pipeline operation in a processor operating by a pipeline processing method. The present invention relates to a method for automatically generating a pipeline operation verification verification instruction sequence for verifying whether or not specifications are realized.

[0002]

2. Description of the Related Art In order to realize a processor having a high processing speed, a pipeline processing method is generally adopted. The pipeline processing method divides the processing of an instruction of a processor into a number of unit operations (hereinafter, referred to as a pipeline stage) that can basically be processed in one clock, and overlaps the execution of successive instructions so as to overlap each pipe. This is a method of processing in parallel at the line stage.

FIG. 9 is a diagram showing a pipeline processing system on which the present invention is based. In FIG.
05 indicates each stage in the pipeline processing, and time 1 to time 6 indicate the lapse of time of the processing.
In the pipeline processing, as shown in the figure, at time 1, instruction 1 is fetched at pipeline stage 1 and at time 2, instruction 1 is decoded at pipeline stage 2 and Instruction 2 is fetched in pipeline stage 1.

Similarly, at time 5, instruction 5 is fetched in pipeline stage 1, and
Instruction 4 is decoded in pipeline stage 2, instruction 3 is executed in pipeline stage 3, memory access of instruction 2 is performed in pipeline stage 4, and pipeline stage 5 is executed. Instruction 1 is written back.

As described above, in the pipeline processing, unit processing of different instructions is performed simultaneously in each pipeline stage at the same time. By the way, in the pipeline processing, a situation in which execution of a preceding instruction prevents execution of a subsequent instruction in an ideal clock cycle is called a hazard.

There are the following three types of hazards in pipeline processing. Structural hazard A situation in which there are instructions (pipeline stages) that cannot be executed simultaneously due to a collision of hardware resources. Data hazard A RAW hazard that attempts to execute an instruction that requires the result before the execution result of the instruction is written, and attempts to execute an instruction that overwrites the same location before reading the required data at a certain location There is a WAR hazard that attempts to write the execution result of a later instruction to the same location before the execution result of the previous instruction is written. Control hazard A situation in which an instruction that is being processed must be rejected by an instruction that changes the value of a program counter (PC).

[0007] The pipeline control section includes many functions of exception handling for the above-mentioned hazard, and in order to verify the hazard, it is necessary to enumerate all types of instruction sequences that cause the hazard and give it to the processor. There is. It is common practice to add a special mechanism to hardware to avoid hazards. In order to verify the logic of the pipeline operation in a processor that achieves such specifications, it is necessary to create not only an instruction sequence for generating a hazard but also an instruction sequence for operating the hazard avoidance mechanism. .

Conventionally, the above-described instruction sequence for logic verification of the pipeline is often manually created based on the specifications of the pipeline. In the case of manually creating the instruction sequence, the creator considers the above points. It is necessary to select an instruction sequence that will do enough.

[0009]

A major problem in creating a logic verification program for a processor is that a standard for determining whether the verification is sufficient has not been established. Therefore, when an instruction sequence is generated at random, it is necessary to guarantee the quality of verification by increasing the number of instructions, and the execution time for verification becomes longer.

[0010] In addition, manual preparation of an instruction sequence requires a lot of time and human cost. Then, there is no guarantee that verification is sufficient in either case of a method of randomly generating an instruction sequence or a method of manually creating an instruction sequence. In particular, for pipeline operation, design errors often occur due to the complexity of the mechanism, and it is difficult to create a logic verification program that covers many errors, even though the logic verification is very important. There was a problem that it is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and a high-quality pipeline verification instruction sequence is automatically generated simply by giving a pipeline specification.
It is another object of the present invention to provide a method of automatically generating a pipeline operation verification instruction sequence that can be generated comprehensively.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. The invention of claim 1 of the present invention, as shown in FIG. 1 (a), the automatic generation method of pipeline operation verification instruction string to verify the pipeline operation processor configured with a pipeline processing method, each The hardware resources shared by the pipeline stages and the
Given a pipeline specification that describes the use status of shared resources in the stage and instructions that use those shared resources, each pipeline and
For all the shared resources shared by the stages, the instruction sequence for verifying the operation of the pipeline control unit is automatically obtained by obtaining all combinations of the instruction sequence in which execution of the previous instruction prevents execution of the subsequent instruction. Is generated.

According to a second aspect of the present invention, in the first aspect, an instruction sequence causing a pipeline structural hazard is automatically generated based on a pipeline specification relating to hardware resources used in each instruction of the processor. It is something to do. According to a third aspect of the present invention, in the first aspect of the present invention, an instruction sequence in which normal execution of data is prevented from being executed by execution of each instruction of the processor is automatically generated based on a pipeline specification.・ Instructions that cause hazards are automatically generated.

According to a fourth aspect of the present invention, in the first aspect of the present invention, a program is stored in each instruction of the processor.
An instruction sequence causing a control hazard is automatically generated based on a pipeline specification relating to a change in the content of a counter. The invention of claim 5 of the present invention provides:
As shown in FIG. 1B, in a method of automatically generating a pipeline operation verification instruction sequence for verifying the operation of a hazard avoiding mechanism of a processor configured by a pipeline processing method, a hazard avoiding mechanism is provided. A first instruction sequence for verifying the operation of the pipeline control unit is automatically generated based on the pipeline specification before the introduction, and the operation of the pipeline control unit is determined based on the pipeline specification after the hazard avoidance mechanism is introduced. A second instruction sequence to be verified is automatically generated, and the first
By comparing the second instruction sequence with the second instruction sequence, an instruction sequence for verifying the operation of the hazard avoiding mechanism is automatically generated.

[0015]

The information characterizing the pipeline operation of the processor is as follows. (1) Hardware resources shared by a plurality of pipeline stages. (2) For each of (1) above, a pipeline stage using hardware resources. (3) For each of the above (2), resource occupation, data reading and writing, instruction fetching with reference to a program counter (PC) (instruction fetch)
And resource usage, such as changes to the program counter (PC). (4) An instruction for executing the operation for each of the above (3).

Using the above information, it is possible to enumerate all the instruction sequences that cause a pipeline hazard. The invention according to claims 1 to 4 of the present invention is based on the specification including the information, and for all the shared resources shared by each pipeline stage, execution of the preceding instruction prevents execution of the subsequent instruction. An instruction sequence for verifying the operation of the pipeline control unit is automatically generated by obtaining all combinations of instruction sequences to be executed, thereby verifying the pipeline operation without human intervention. An instruction sequence can be generated comprehensively and automatically.

According to a fifth aspect of the present invention, a first instruction sequence for verifying the operation of a pipeline control unit is automatically generated based on a pipeline specification before a hazard avoiding mechanism is introduced, and a hazard hazard is automatically generated. By automatically generating a second instruction sequence for verifying the operation of the pipeline control unit based on the pipeline specification after the introduction of the avoidance mechanism, and comparing the first instruction sequence with the second instruction sequence, It is possible to generate a sequence of instructions for verifying the operation of the line hazard avoidance mechanism without manual intervention.

[0018]

FIG. 8 is a diagram showing an example of a specification of a pipeline operation, and FIG. 8A is a diagram showing an example of a specification of a pipeline operation without a hazard avoidance mechanism. FIG. 4B is a diagram illustrating an example of specifications of a pipeline operation having a hazard avoidance mechanism.

The specification description shown in FIG. 8A means the following items. “Registers”, which are hardware resources, are read in pipeline stage 2 and written in pipeline stage 5. In the above, the register is occupied during reading of the register in the pipeline stage 2 and writing cannot be performed by another instruction in the pipeline stage 5. Similarly, pipeline stage 5
The register is occupied during the writing of the register in, and reading by another instruction in the pipeline stage 2 cannot be performed. Instructions related to reading registers in pipeline stage 2 are “ALU” related instructions (eg,
An addition instruction “ADD”) and a “Store” instruction. Instructions related to register writing in pipeline stage 5 include “ALU” -related instructions,
This is a “Load” instruction. An instruction fetch is performed in a pipeline stage 1 for a “program counter (hereinafter, referred to as a PC)” which is a hardware resource.
The contents of C are changed. In the above, the PC is occupied during the instruction fetch in the pipeline stage 1 and cannot be written by another instruction in the pipeline stage 4. Similarly, the PC is occupied during the change of the contents of the PC in the pipeline stage 4, and the instruction fetch by another instruction in the pipeline stage 1 cannot be performed. The instructions related to the instruction fetch of the PC in the pipeline stage 1 are all instructions, and the instructions related to the change of the contents of the PC in the pipeline stage 4 are “Branch” instructions.

The specification description shown in FIG.
In the above, the condition of "occupation" of the register is avoided by the hazard avoiding mechanism. In other words, even while the register is being read in the pipeline stage 2, writing can be performed by another instruction in the pipeline stage 5, and similarly,
Even when a register is being written in the pipeline stage 5, reading by another instruction can be performed in the pipeline stage 2, and other specifications are the same as those in FIG. It is.

FIGS. 2 to 5 are flow charts showing an embodiment of the present invention. The embodiment of the present invention will be described with reference to FIG. 8A using an example of the specification description shown in FIG. In FIG. 2, in step S21, the shared resource R is selected. In the example of FIG. 8A, since the shared resource R is “register” or “PC”, any one of the resources is selected.

In step S22, two pipeline stages Si and Sj (i <
Select j). For example, if “register” in FIG. 8A is selected in step S21, step S2
In the stage 2, Si = 2 as the stage Si,
Also, Sj = 5 is selected as the stage Sj.

For example, in step S21,
If “PC” in FIG. 8A is selected, step S22
In (2), Si = 1 is selected as the stage Si, and Sj = 4 is selected as the stage Sj. Next, in step S23, an instruction sequence that causes a structural hazard for the shared resource R between the pipeline stages Sj and Si is generated and output.

FIG. 3 is a flowchart showing the contents of the processing in step 23. The processing in step 23 will be described with reference to FIG. In step S31,
It is determined whether or not the pipeline stages Sj and Si occupy the shared resource R. In the example of FIG. 8A,
Since both the register and the PC occupy resources, step S3
Go to 2.

If the shared resource is not occupied in step S31, the process returns to the flowchart of FIG. 2 and goes to step S24. In step S32, an instruction A occupying the shared resource R at the pipeline stage Si and an instruction B occupying the shared resource R at the pipeline stage Sj are selected. In the example of FIG. 8A, if the shared resource is a register, in step S32, for example, a "Store" instruction that occupies the register in the pipeline stage 2 is selected as the instruction A,
As the instruction B, a “Load” instruction that occupies a register in the pipeline stage 5 is selected.

In step S33, (j-
i) Output an instruction sequence for executing the instruction B before the instruction. FIG.
In the example of (a), if the shared resource is a register as described above, the instruction A, for example, (5) of the “Store” instruction
-2) Before the instruction, ie, three instructions before the instruction B, for example,
An instruction sequence for executing the “Load” instruction is output. In step S34, it is determined whether or not all the combinations of the instruction A and the instruction B have been processed. If not, the process returns to step S32 and the above processing is repeated, and the processing has been completed for all the combinations. In this case, the process returns to the flowchart of FIG. 2 and proceeds to step S24.

In step S24, the pipeline
An instruction sequence that causes a data hazard for the shared resource R between the stages Sj and Si is generated and output. FIG. 4 is a flowchart showing the processing contents in step 24,
The process in step 24 will be described with reference to FIG. In step S41, it is determined whether or not the pipeline stages Si and Sj read and write data of the shared resource R.

In the case where the pipeline stages Si and Sj do not read or write data of the shared resource R, FIG.
Returning to the flowchart of, the process goes to step S25. When the pipeline stages Si and Sj read and write the data of the shared resource R, the procedure goes to step S42, where the instruction A for reading and writing the data of the shared resource R and the pipeline stage Sj at the pipeline stage Si. Select an instruction B for reading and writing data of the shared resource R.

In the example of FIG. 8A, if the shared resource is a register, at step S42, for example,
In the pipeline stage 2 as instruction A, "Stor
The “e” instruction is selected, and the “Load” instruction is selected in pipeline stage 5 as instruction B. Next, in step S43, it is determined whether at least one of the instructions A and B is a write. If at least one of the instructions A and B is not a write, the process proceeds to step S45.

If one is a write, step S44
And outputs an instruction sequence for executing the instruction B before the instructions 1 to (ji-1) of the instruction A. For example, in step S42, as described above, the “Store” instruction is selected as the instruction A in the pipeline stage 2;
"Load" in pipeline stage 5 as instruction B
If an instruction is selected, go to step S44,
1 to (5-2-1) instructions before the "Store" instruction, that is, "L" one instruction before and two instructions before the "Store" instruction.
An instruction sequence for executing the “oad” instruction is output.

After outputting the instruction sequence as described above, it is determined in step S45 whether or not all combinations of instruction sequences have been processed. If all combinations have not been processed, the process returns to step S42. And the above processing is repeated. When all the combinations have been processed, the process returns to the flowchart of FIG. 2 and proceeds to step S25.

In step S25 of FIG. 2, it is determined whether or not the shared resource R is a program counter (PC).
If the shared resource R is not a program counter (PC), the procedure goes to step S27. If the shared resource R is a program counter (PC), step S26
And outputs an instruction sequence causing a control hazard between the pipeline stages Si and Sj.

FIG. 5 is a flowchart showing the contents of the processing in step 26, and the processing in step 26 will be described with reference to FIG. In step S51,
Instruction fetch is performed at the pipeline stage Si, and it is determined at the pipeline stage Sj whether to change the PC. If not, the process returns to the flowchart of FIG. 2 and proceeds to step S27.

When fetching an instruction at the pipeline stage Si and changing the PC at the pipeline stage Sj, the procedure goes to step S52, where an instruction B for changing the PC is selected at Sj. In FIG. 8A, “Br
The instruction "Branch" is selected as instruction B because the "anch" instruction changes the PC in pipeline stage 4.

In step S53, one of the arbitrary instructions
An instruction sequence for executing the instruction B is output before the instructions (.about. (Ji-1)). In FIG. 8A, an instruction is fetched in the pipeline stage 1 and the PC is changed in the pipeline stage 4, so that arbitrary instructions 1 to (4-1)
-1) An instruction sequence for executing the “Branch” instruction is output before the instruction, that is, one instruction before and two instructions before any instruction.

In step S54, it is determined whether or not processing has been performed for all cases of the instruction B. If processing has not been performed for all cases, the process proceeds to step S5.
2 and the above process is repeated. If all cases have been processed, the process returns to the flowchart of FIG. 2 and proceeds to step S27.

In step S27 of FIG. 2, it is determined whether or not the above processing has been performed for all combinations of the pipeline stages Si and Sj. If not, the flow returns to step S22 to repeat the above processing. . Also,
If the above processing has been performed for all combinations of the pipeline stages Si and Sj, the process proceeds to step S28, and it is determined whether the above processing has been performed for all shared resources.

If the processing has not been performed for all the shared resources, the process returns to step S21, and the above processing is repeated. When the processing has been completed for all the shared resources, the processing ends. FIG. 6 shows a register structure hazard (FIG. 8A), a register data hazard (FIG. 8B), and a PC structure generated in the pipeline processing of the specification description of FIG. It is a figure which shows the instruction sequence for verification of a hazard ((c) of the same figure) and a control hazard ((d) of the same figure), In the same figure, "ALU" is the above-mentioned, for example, the instruction "ADD" etc. This means an operation-related instruction, and "-" means an appropriate instruction that does not disturb the pipeline operation.

As shown in the drawing, as the instruction sequence for verifying the pipeline processing of the specification description of FIG. 8A, an instruction sequence of A1 to A4 is generated for the register structural hazard, and the data of the register is stored. It is B1 about hazard
The instruction sequence of B8 is generated, the instruction sequence of C1 is generated for the PC structural hazard, and the instruction sequences of D1 and D2 are generated for the control hazard.

FIGS. 7A, 7B, and 7C show the pipeline processing of the specification described in FIG. 8B, "the register can be read and written simultaneously", generated by the above-described procedure. FIG. 7 is a diagram showing an instruction sequence for verifying the ALU. In FIG. 6, “ALU” and “−−−” are the same as in FIG.
Operation-related instructions, which are appropriate instructions that do not disturb the pipeline operation.

As is clear from FIGS. 7A, 7B and 7C, in the pipeline processing of the specification description in FIG. 8B, the condition of "occupancy" of the register is determined by the hazard avoiding mechanism. Therefore, an instruction sequence for verifying the structural hazard of the register is not generated, and FIG.
(B) and (C), a sequence of instructions B11 to B18 for the data hazard of the register, a sequence of instructions C11 for the structural hazard of the PC, a sequence of instructions D11 for the control hazard,
D12 is generated.

FIG. 7D shows a sequence of instructions E1 to E4 for operating the hazard avoiding mechanism which makes it possible to simultaneously read and write registers in the pipeline processing of the specification description of FIG. 8B. FIG. 6 shows “ALU” and “−−−” as in FIG.
Operation-related instructions, which are appropriate instructions that do not disturb the pipeline operation.

The instruction sequence of FIG. 7D is the same as the instruction sequence of FIG.
It can be obtained from the difference between the instruction sequences in FIGS. 7A, 7B, and 7C. As is apparent from FIGS.
The instruction sequence for operating the hazard avoiding mechanism of (d) is shown in FIG.
(A) It is equal to the instruction sequence for verifying the structural hazard of the register.

[0044]

As is apparent from the above description,
According to the present invention, it is possible to automatically generate an instruction sequence for verifying the operation of the pipeline control unit based on the pipeline specification, so that a high-quality logic capable of comprehensively verifying the pipeline operation is provided. A logic verification program that can automatically generate a verification program, generates many design errors due to the complexity of its mechanism, and covers many possible errors despite the importance of logic verification Can be automatically created without the need for manual operations.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a flowchart (part 1) illustrating an embodiment of the present invention.

FIG. 3 is a flowchart (part 2) showing the embodiment of the present invention.

FIG. 4 is a flowchart (part 3) showing the embodiment of the present invention.

FIG. 5 is a flowchart (part 4) showing the embodiment of the present invention.

FIG. 6 is a diagram showing an example of an instruction sequence generated according to the embodiment of the present invention.

FIG. 7 is a diagram (continued) showing an example of an instruction sequence generated by the embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a pipeline specification.

FIG. 9 is a diagram showing an example of a pipeline process which is a premise of the present invention.

[Explanation of symbols]

101, 102, 103, 104, 105 Pipeline stage

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/38 G06F 11/22-11/28

Claims (5)

(57) [Claims] 1. A method of automatically generating a pipeline operation verification instruction sequence for verifying a pipeline operation of a processor configured by a pipeline processing method, comprising: a hardware resource shared by each pipeline stage; Given a pipeline specification that describes the usage status of shared resources in each pipeline stage and instructions that use those shared resources, all shared resources shared by each pipeline stage are based on the above pipeline specifications. For a resource, an instruction sequence for verifying the operation of the pipeline control unit is automatically generated by obtaining all combinations of instruction sequences in which execution of a previous instruction prevents execution of a later instruction. Automatic generation method of instruction sequence for pipeline operation verification. 2. A pipeline operation verification system according to claim 1, wherein an instruction sequence causing a structural hazard of the pipeline is automatically generated based on a pipeline specification regarding hardware resources used in each instruction of the processor. automatic generation method of instruction sequence. 3. An instruction sequence causing a data hazard is automatically generated based on a pipeline specification by automatically generating an instruction sequence in which execution of each instruction of a processor prevents normal reading and writing of data. 2. The method for automatically generating a pipeline operation verification instruction sequence according to claim 1, wherein: 4. The pipeline operation verification system according to claim 1, wherein an instruction sequence causing a control hazard is automatically generated based on a pipeline specification relating to a change in the contents of a program counter in each instruction of the processor. automatic generation method of instruction sequence. 5. A pipeline processing method pipeline operation automatic generation method of the verification instruction string to verify the operation of the processor configured hazard avoidance mechanism, the pipe on the basis of pipeline specifications prior to introduction of the hazard avoidance mechanism A first instruction sequence for verifying the operation of the line control unit is automatically generated, and a second instruction sequence for verifying the operation of the pipeline control unit is automatically generated based on the pipeline specification after the introduction of the hazard avoidance mechanism. And an instruction sequence for verifying the operation of the hazard avoidance mechanism is automatically generated by comparing the first instruction sequence with the second instruction sequence. Automatic generation method .