JPS58179995A - 半導体記憶装置 - Google Patents
半導体記憶装置Info
- Publication number
- JPS58179995A JPS58179995A JP57062961A JP6296182A JPS58179995A JP S58179995 A JPS58179995 A JP S58179995A JP 57062961 A JP57062961 A JP 57062961A JP 6296182 A JP6296182 A JP 6296182A JP S58179995 A JPS58179995 A JP S58179995A
- Authority
- JP
- Japan
- Prior art keywords
- word line
- address change
- address
- thyristor
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015654 memory Effects 0.000 claims abstract description 28
- 238000001514 detection method Methods 0.000 claims description 30
- 230000005669 field effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 239000000872 buffer Substances 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57062961A JPS58179995A (ja) | 1982-04-15 | 1982-04-15 | 半導体記憶装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57062961A JPS58179995A (ja) | 1982-04-15 | 1982-04-15 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58179995A true JPS58179995A (ja) | 1983-10-21 |
JPS6137702B2 JPS6137702B2 (enrdf_load_stackoverflow) | 1986-08-25 |
Family
ID=13215422
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57062961A Granted JPS58179995A (ja) | 1982-04-15 | 1982-04-15 | 半導体記憶装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58179995A (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02177096A (ja) * | 1988-12-27 | 1990-07-10 | Nec Corp | プログラマブル半導体集積回路 |
JP2010050456A (ja) * | 2008-08-20 | 2010-03-04 | Intel Corp | プログラマブル・リード・オンリ・メモリ |
-
1982
- 1982-04-15 JP JP57062961A patent/JPS58179995A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02177096A (ja) * | 1988-12-27 | 1990-07-10 | Nec Corp | プログラマブル半導体集積回路 |
JP2010050456A (ja) * | 2008-08-20 | 2010-03-04 | Intel Corp | プログラマブル・リード・オンリ・メモリ |
Also Published As
Publication number | Publication date |
---|---|
JPS6137702B2 (enrdf_load_stackoverflow) | 1986-08-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10242733B2 (en) | Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage | |
US6424586B1 (en) | Semiconductor integrated circuit device and method of activating same | |
US6256239B1 (en) | Redundant decision circuit for semiconductor memory device | |
US5463585A (en) | Semiconductor device incorporating voltage reduction circuit therein | |
US6791897B2 (en) | Word line driving circuit | |
US8391097B2 (en) | Memory word-line driver having reduced power consumption | |
JP2507164B2 (ja) | 半導体記憶装置 | |
JPH02166695A (ja) | スタチックランダムアクセスメモリ装置 | |
US6414895B2 (en) | Semiconductor memory device with reduced standby current | |
KR19980080153A (ko) | 고속 기입 회복을 하는 메모리 장치 및 고속 기입회복 방법 | |
US4587639A (en) | Static semiconductor memory device incorporating redundancy memory cells | |
US7092309B2 (en) | Standby mode SRAM design for power reduction | |
US10878853B2 (en) | Power supply control | |
CN113284526B (zh) | 电子器件及其操作方法 | |
US7489582B1 (en) | Low overhead switched header power savings apparatus | |
US5337273A (en) | Charge sharing flash clear for memory arrays | |
JPS58179995A (ja) | 半導体記憶装置 | |
JPH0612626B2 (ja) | 半導体メモリ装置 | |
US5469385A (en) | Output buffer with boost from voltage supplies | |
JPH06508233A (ja) | 差動ラッチングインバータ及びこれを用いるランダムアクセスメモリ | |
TWI782693B (zh) | 記憶體裝置及其操作方法 | |
JPH07182869A (ja) | 半導体記憶装置のデータ書き込み方法及び半導体記憶装置 | |
JPS6138560B2 (enrdf_load_stackoverflow) | ||
JP3266346B2 (ja) | 半導体記憶装置 | |
JPH0676593A (ja) | 半導体メモリ装置 |