JPS58178551A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an IC which operates at a high speed in a high density by forming a resistance layer in a semiconductor device made of a bipolar IC with N or P type polycrystalline Si while forming it vertically to the surface of a substrate in long shape in a longitudinal direction when forming the layer. CONSTITUTION:An N type buried collector layer 3 is formed while enclosing with a P type buried layer 2 on a P type Si substrate 1, an N type layer 4 is epitaxially grown on the layer 3, a P type base layer 5 is formed on the surface, and an N type emitter domain 6 is diffused in the layer 5. Then, the layers 4, 5 are surrounded by an insulating film 9, a window is opened, and base and emitter electrodes 11, 10 are respectively mounted on the domain 5, 6. Thereafter, a resistance layer 22 made of N or P type polycrystalline Si which is vertical and intruded into the layer 3 is buried in the film 9 through another window, and a resistance electrode 21 is covered on the layer 22. In this manner, the area which is occupied with the layer 22 is approx. 1/10 of normal value, thereby increasing the density of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly, to a high-density Kashima velocity table bipolar IC and a method for manufacturing the same.

Figure 81 shows T'rL, one of the conventional bipolar ICs.
FIG. 2 shows a cross section of the structure of the transistor T3 and resistor R3 in the standard circuit of FIG. 1 when realized by a conventional manufacturing method.

In Figure 2, 1 is a p-type substrate, 2 is pm! m layer, 3
is the collector layer including 11, and 4 is the n-type epitaxy.
, 5 up fJ diffusion layer and transistor pace,
6 is 11! II diffusion layer is the emitter of the transistor, 7 is a deep collector diffusion layer, 8 is a p-type paper layer, 9 is an insulating film, 10, 11.12 are emitter electrodes, space electrodes, collector electrodes, and 13.14 are resistor electrodes. It is. Note that the collector electrode 12 is electrically connected to the resistance electrodes 13 and 14 by metal wiring (not shown).

In the above configuration, the conventional bipolar IC has a structure in which a resistance region, that is, a region mainly consisting of the p-layer resistance layer 8, is provided in the horizontal direction, which hinders high density. For example, the planar dimension of the resistor is length/41! If the ratio is 10/l, 411i is 5μms determined by photolithography.
The length is 50μm and the area is 5X50J-
becomes. Previously, the resistance region formed a pn junction with the n-type region, and the junction capacitance was large, which hindered speeding up. Furthermore, in the conventional structure as described above, it is necessary to take out the collector electrode, which generally requires an area of at least about 50 .mu.♂, which hinders high density.

An object of the present invention is to eliminate these drawbacks by using an n-type polysilicon layer or an up-type polysilicon layer as a resistance layer in the vertical direction, and will be described in detail below.

Two embodiments of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 shows a first embodiment of the present invention, which implements the transistor T3 and resistor R3 shown in FIG. 1 above. In the figure, the same reference numerals as in FIG. 21 is a pace electrode, 22 is an n-type polysilicon layer in contact with the lower part of the pace electrode 21, and the p-type silicon substrate 1
It is formed to be long in the vertical direction perpendicular to the plane of the n-type buried collector layer 3 and is electrically connected to the n-type buried collector layer 3.

In the above configuration, according to one embodiment of the present invention, the structure of the transistor T3 and the resistor R3 provided in the TTL, which is one of the PIPs 2, is obtained. p! At the same time, it can perform the function of the deep collector diffusion layer 7 by being electrically connected to the n-type buried collector layer 3.

As explained above, in the first embodiment, the deep collector diffusion layer 7, the pWi resistance layer 8, the collector electrode 12, and the resistance electrodes 13 and 14 are removed from the conventional example described above.
Since the resistor electrode 21 and the n-type polysilicone 7 layer 22t are constructed in the ninth embodiment, there are the following advantages.

(1,) Because the resistive layer is used vertically, i.e. the substrate l
Since it is used in a direction perpendicular to the plane of
It can be configured as follows, and is less than the conventional 5×50μ, that is, about 1/10.

(2) There is no need to provide the collector electrode 12.

(3) The resistance layer 22 is sufficiently surrounded by the insulating film 9 on all sides, so that the capacitance is relatively small.

(4) All of the l11rTi of the pace diffusion layer 5 is the insulating film 9
Rounding in contact with , the pace-collector junction capacitance becomes smaller.

Therefore, the first embodiment has the great effect of significantly increasing density and speed.

In the first embodiment, one end of the resistor was connected only to the collector, but if the structure shown in FIG.
As an example, one end of the n-type polysilicon 7 layer 22, which is a resistor, can be made tangential to the n-type buried collector layer 3 and the paste of another transistor (not shown). In this case, it is necessary to provide the deep collector diffusion layer 7 and take out the collector electrode 12 as in FIG. Similarly, the second embodiment shown in FIG. 4 has the effect of increasing density and speed, and in the standard circuit of FIG. 1, the resistor R2 and transistor T2 are realized.
The resistive electrode 22 is electrically connected to the power supply Vcc, and the collector electrode 12 is electrically connected to the pace of the transistor T3.

In the above two embodiments, the n-type polysilicon 7 layer 22 is used as a resistor, but if the transistor connected to the resistor is a pnp type, this resistor is of course a p-type polysilicon layer, and the above two embodiments In this example, an IIC p-type polysilicon layer is used instead of an n-type polysilicon layer.

Next, manufacturing methods of two embodiments of the present invention will be explained.

The manufacturing method of the present invention is carried out in the normal Nybora manufacturing process, and before the epitaxial growth, the polysilicon is first grown on the part where it is desired to grow, for example, in the first embodiment shown in FIG. Debo-knot a thin layer of polysilicon. During the next epitaxial growth, a polysilicon layer 22 is grown directly on top of the debossed polysilicon. Thereafter, n-type diffusion into the polysilicon layer 22 is performed after pace diffusion or emitter diffusion. Inside this polysilicon layer 22, the diffusion rate is fast, and low-temperature treatment is now possible, and fluctuations in transistor characteristics can be suppressed to a minimum. In this way, it is easy to form a high-density structure in which the n-type polysilicon 7 layer 22, which is a resistor, is vertically connected and partially connected to the n-type buried collector layer 3.
It is possible to manufacture high-speed ・9 Ibora ICs.

As described above, the present invention provides a bipolar IC in which an n-type polysilicon layer or a p-type polysilicon layer is formed as a resistor layer in a vertical structure perpendicular to the substrate surface, and one end of this resistor is connected to a buried collector layer. By doing this, it is possible to achieve high density and high speed, and this manufacturing method can be applied to all bipolar ICs that adopt the epitaxial process.It has a unique effect in terms of both performance and manufacturing method. It has the following.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit diagram of TTL, Fig. 2 is a structural sectional view of a conventional bipolar device, Fig. 3 is a diagram corresponding to Fig. 2 showing the first embodiment of the present invention, and Fig. 4 is a diagram of the structure of a conventional bipolar device. FIG. 2 is a diagram corresponding to FIG. 2 showing a second embodiment. 1...p-type silicon substrate, 2...p-type buried layer, 3...
... n-type buried collector layer, 4... n-type epitaxial layer, 5... p-type base layer, 6... n-type epitaxial layer,
7... Deep collector diffusion layer, 8... P-type paper layer, 9... Insulating film, 10... Emitter electrode, 11...
・Pace electrode, 12...Collector electrode, 13.14・
. . . Resistance electrode, 21 . . . Resistance electrode, 22 . . . N-type polysilicon layer. Special fraud applicant Oki Electric Industry Co., Ltd.? 1 Figure 2 Figure 3 Figure 4 Procedural Amendment September-3, 1980 Director General of the Patent Office ``tI41 + Kazuo 1, Indication of the Case 1981 Request No. 60874 2, @
@t) 4th person conductor device and its conductor device 3, relationship with the case of the person making the amendment Hiroshi Tatami Applicant (029) Oki Electric Industry Co., Ltd. Kinsha 4, Agent 5, Date of amendment order Showa year Month Day (Yu@) 6, Subject of correction@-book (D r@@0Wla*Explanation J 0IIIA. (1) "Resistive electrode 13" on page 2, lines 12-13 of the specification
"14 is not shown" is corrected to "resistance electrode 13 is not shown." (2) “Pace electrode” on page 3, lines 16 and 17 of the same book t-
Correct it to "resistance electrode." (3) Delete "And for what it's worth" on page 4, line 19 of the same book. (4) Corrected "Resistance electrode zzJt-1 resistance electrode 21" on page 5, line 16 of the same book. that's all

Claims (2)

[Claims] (1) A semiconductor device composed of a bipolar IC, which is characterized by using an n-type polysilicon layer or a p-type polysilicon layer as a resistance layer and disposing it long in the vertical direction perpendicular to the substrate surface. . (2) In a semiconductor device manufacturing method using a normal bipolar manufacturing process, a thin layer of polysilicon is deposited in the area where polysilicon is desired to be grown before epitaxial growth, a polysilicon layer is formed during the next epitaxial growth, and then paced diffusion is performed. Alternatively, a method for manufacturing a semiconductor device, characterized in that n-type diffusion into the polysilicon layer is performed after emitter diffusion.