JPS58161372A - Manufacture of mos integrated circuit - Google Patents

Abstract

PURPOSE:To form a high melting point metallic silicide layer on the surface of an Si film in self-alignment by a method wherein a gate insulation film and an Si film are formed on the main surface of an Si semiconductor, and etched by leaving a wiring region, and a high melting point metallic layer is formed over the entire surface. CONSTITUTION:Using a P type Si substate 11, field oxide films 12 are formed. Next, after forming a gate oxide film 13, the surface 14 of the Si substrate which should be formed as a direct contact region is exposed. Then, after forming the polycrystalline Si film, etching is performed except for the part 15 for gate wiring. Further, an Mo film 16 is formed. Thereafter, the Si 15 and the Mo 16 are mixed, and thus a drain 19 and a source 20 are formed. A heat treatment is performed in an H2 gas atmosphere, and accordingly an Mo silicide layer 17 is formed only on a polycrystalline Si layer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing MO8 integrated circuits. As the density of MO8 integrated circuits increases, it is well known that signal propagation delays caused by wiring resistance in gate wiring sections have become a major limiting factor for high-speed operation of large-scale integrated circuits. As a way to solve this problem, instead of the conventional polycrystalline silicon gate wiring, so-called polycide gate wiring technology, which uses a two-layer structure in which a high melting point metal silicide layer is formed on polycrystalline silicon, is being considered. It has been. The steps in the conventional manufacturing process for polycide gate structures include growing an insulating film on one main surface of a semiconductor substrate, etching the area of the insulating film that should be a direct contact, and then etching a predetermined film doped with impurities. A method of growing thick polycrystalline silicon and then forming a silicide of a refractory metal on the polycrystalline silicon by simultaneous evaporation of electron beam evaporation or sputtering, or depositing a refractory metal layer using the various film formation methods described above. There is a known method in which a high melting point metal silicide is formed on the polycrystalline silicon by heat treatment. However, these manufacturing methods have the following drawbacks. That is, in the former method, after forming a silicide layer of a high-melting point metal on the top surface of a polycrystalline silicon film, there is a step of patterning the gate electrode and wiring by the usual method using a photoresist as a mask. At this time, in order to uniformly etch the high melting point metal silicide, it is important to make the high melting point metal silicide sufficiently uniform.

An annealing process at about 1000°C is required. However, during this annealing, impurities such as phosphorus doped in the polycrystalline silicon diffuse to the outside through the silicide layer, making it impossible to form a good direct contact. However, it has been reported that covering the upper part with an oxide film or the like and annealing it is effective in preventing this diffusion, but the disadvantage is that the process becomes complicated. Furthermore, when patterning the two-layered structure of Fi using the former method, since the etching rates of the refractory metal silicide and polycrystalline silicon are not the same, the silicide and polycrystalline silicon are etched in a self-aligned manner. There are drawbacks (3) that make it difficult to do so. On the other hand, in the latter method, in addition to the above-mentioned drawbacks regarding patterning, there are also drawbacks in the uniformity of the high melting point metal silicide formed by heat treatment and in the reproducibility of the silicide reaction. That is, the silicide reaction between polycrystalline silicon doped with impurities at a high concentration and a high melting point metal is often significantly reduced compared to the reaction when polycrystalline silicon is not doped with impurities at a high concentration. The reason for this is thought to be the effects of a natural oxide film formed on the surface of polycrystalline silicon and oxygen incorporated as an impurity into the high melting point metal, but these factors may have subtle effects due to manufacturing conditions. varies greatly between lofts due to the impact received. Therefore, it has been considered difficult to form a refractory metal silicide layer with a uniform thickness on polycrystalline silicon doped with high concentrations of impurities using only the heat treatment method described above with good reproducibility. be.

In view of the above-mentioned circumstances, an object of the present invention is to provide two layers in which a high melting point metal silicide layer and a polycrystalline silicon layer are formed in a self-aligned manner.
This provides a simple manufacturing method for an MO5 integrated circuit using a layered structure as a gate electrode wiring (4), in which a silicon film coated with an insulating film is formed on one main surface of a semiconductor substrate of a first conductivity type. The silicon film is etched leaving areas to be used as direct contacts, gate electrodes, and wiring, thereby forming a high melting point metal layer on the entire surface or only on the surface of the silicon film, and etching the metal layer from the top surface of the layer. After mixing the high-melting point metal layer and the silicon film and implanting an impurity exhibiting the second conductivity type under the conditions that the impurity reaches the surface of the semiconductor substrate in the regions that will later become source and drain electrodes, It is characterized by performing heat treatment.

Hereinafter, a typical embodiment of the present invention will be described in detail using the drawings.

Figures (a) to (d) are schematic cross-sectional views showing one example of the manufacturing process of the present invention.

In FIG. 1A, first, a field oxide film 12 is formed using a P-type 5i substrate 11 by a conventional selective oxidation method. Next, a gate oxide film 13 of 300 people was deposited using a thermal oxidation method.
After forming the 5i substrate surface 14, which is to be a direct contact area, is exposed by a conventional photoetching method. Next, as shown in Figure (b), after forming a polycrystalline silicon film containing phosphorus as a dopant and having a thickness of 3000×, 1 the polycrystalline silicon is etched except for the gate electrode wiring portion 15 by a normal photoetching method. do.

Furthermore, as shown in Figure (C), a Mo film 16 with a film thickness of 4ooX is formed by electron gun deposition. After that, A: polycrystalline silicon 15 and M are implanted by implanting ions at a dose of 10''m2 at an acceleration voltage of 30Qkav.

16 to form a drain 19 and a source 20 shown in FIG. Thereafter, heat treatment is performed at 600° C. for 20 minutes in a hydrogen gas atmosphere. Through this heat treatment, a 1000A thick M film is formed only on the polycrystalline silicon layer 18.
An O silicide layer 17 is formed.

Next, a process is performed for about 30 seconds using a hydrogen peroxide-based etching solution. At this time, unreacted Mo on the oxide film is etched away, but since MO silicide is stable against this etching solution, As shown in Figure (d), a two-layer structure electrode is obtained in which MO silicide 17 is formed in a self-aligned manner only on the top of the polycrystalline silicon layer. The MO silicide layer formed by this manufacturing method had significantly improved uniformity and flatness compared to the MO silicide layer formed only by the heat treatment described above. In addition, the sheet resistance of the two-layer gate wiring manufactured according to this example was 4.
The resistance was about Ω/mouth, and low resistance was achieved. Furthermore, the sheet resistance of the two-layer gate wiring formed according to the present invention has good uniformity within the wafer, and silicide formation using ion implantation has a higher uniformity and resistance than when conventional heat treatment is used alone. Significant effect on reproducibilityf)
Rukoto has been shown.

Note that in this example, the high melting point metal layer is MO.
Although the case using a membrane was described, w,'ra.

Similar reduction in resistance has been achieved with other high melting point metals such as TI. Although we have described the case of AS as the impurity for fc1 ion implantation, similar effects were obtained when impurities such as P and B were used.

[Brief explanation of the drawing]

Figures (a) to (d) are schematic cross-sectional views showing an example of the manufacturing process of an MO5 integrated circuit obtained by the manufacturing method of the present invention. The main symbols in the diagram indicate the following. 11, P-type silicon substrate, 12 field oxide film 1
6. Gate oxide film, 14. Exposed silicon surface where direct contact is to be formed, 15. Polycrystalline silicon gate wiring 16, MO film, 17. MO silicide, 18 Polycrystalline silicon gate wiring, 19 Drain, 21 Direct contact patent applicant NEC Corporation Procedural Amendment (,e) 1. Display of case 1981 Patent Application No. 199
No. 23 No. 2, Title of the invention: Method for manufacturing MOB integrated circuits 3, Relationship to the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4; Agent Address: 37-8 Shiba 5-chome, Minato-ku, Tokyo 108 Residents: Mita Building A two-stage heat treatment method that performs higher heat treatment is being carried out 5
, Claims column of the specification subject to amendment. Detailed description of the invention in the specification. 6. Contents of amendment (1) The scope of claims is amended as shown in the attached sheet. (2) Lines 8 to 9 of page 5 of the specification)! 51, the phrase "or only on the surface of the silicon film" is deleted. (3) From line 13 to line 14 of page 5 of the specification, the phrase “r600'0 degree of kneading or higher” has been replaced with “400°C to 600°C.
After heat treatment at 0°C, a refractory metal silicide layer is formed on the exposed silicon surface in a self-aligned manner by etching away the unreacted refractory metal, and then etched at 800° in a non-reducing gas atmosphere. "C or higher" is corrected. (4) Between the 14th line and the 15th line of page 5 of the specification,
Insert the following sentence. In the method of the present invention, after performing ion implantation,
Heat treatment was performed at a relatively low temperature of 0°C, and then, after removing unreacted high-melting point metals, the temperature was 800°C (1). is extremely important in forming a uniform and smooth high melting point metal silicide in a self-aligned manner on the silicon film surface. That is, the first annealing after ion implantation is performed for example 8
If it is carried out at a high temperature of about 00° C. or higher, silicide will be formed protruding around the surface of the silicon film. Therefore, after first performing annealing at a low temperature, the unreacted high melting point metal is removed to form a silicide in self-alignment with the silicon film surface. The reason for limiting the temperature range is that 400°C is the minimum temperature at which the mixed layer of high melting point metal and 8i formed by ion implantation becomes silicide, and 600°C is the minimum temperature at which the mixed layer of 8i and high melting point metal formed by ion implantation becomes a silicide. This is because this is the upper limit temperature at which no silicide is formed. Thereafter, heat treatment at about 800° C. or higher is performed for the purpose of reducing the resistivity of the silicide layer and electrically activating the implanted ions. If this heat treatment is performed in a reducing gas atmosphere containing H gas, many defects such as pinholes will be formed in the silicide formed by the low temperature heat treatment, making it unsuitable for use in integrated circuits. . Therefore, non-reducing gas atmospheres such as nitrogen, inert gases, oxygen,
In order to maintain the uniform and smooth properties of the silicide, it is important to perform the heat treatment at 800° C. or higher in a gas atmosphere of water vapor or a combination thereof, or in a vacuum. ” (5) “Film thickness 4ooA J” on page 6, line 9 of the specification is corrected to “film thickness 600Aj.” (6) After “Deru” on page 7, line 4 of the specification Insert the following sentence. [However, MoS1 at this point
The sheet resistance on one side is about 50Q/mouth, which is not low enough. Next, heat treatment is performed at 800° C. or higher in a non-reducing gas atmosphere, such as nitrogen gas, for the purpose of reducing sheet resistance. (7) Page 7, line 9, 1-4 of the specification
Correct the text ``Ω/mouth'' to ``7-8 Ω/mouth.'' Agent Patent Attorney Shinbetsu Uchihara Paper 2, Claims (1) After growing an insulating film on one main surface of a semiconductor substrate of the first conductivity type and providing a desired opening in the insulating film, the semiconductor substrate A silicon film doped with a second conductivity type impurity is formed on one main surface, and etching is performed on the silicon film, leaving areas to be used as direct contacts, gate electrodes, and wiring, and a striped melting point metal layer is formed on the entire surface. The high melting point metal layer and the silicon film are mixed from the upper surface of the layer, and the second conductivity type is heat-treated with a strip that reaches the surface of the semiconductor substrate in areas that will later become source and drain electrodes. A method of manufacturing an MOS integrated circuit, comprising: (4) Procedural amendment (method) % formula % 1. Indication of case 1981 Patent Application No. 199
No. 23 No. 2, Title of the invention: Method for manufacturing MO8 integrated circuits 3, Relationship with the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4; Agent 5, date of amendment order May 25, 1980 (shipping date) 6, column for detailed explanation of the invention and brief explanation of drawings in the specification subject to amendment, drawing 7, contents of amendment (1) On page 5, line 17 of the specification, “Figures (a) to (d) are”
Correct the statement "Figures 1 (a) to (d) are". (2) On the 199th line of the same page, replace "In figure (a)" with "
In FIG. 1(a)," the correction is made as follows. (3) On page 6, line 4 of the detailed description, replace the phrase “in figure (b)” with “
``In Figure 1 (b)'', line 9 of the same page, ``Figure (C)'' is replaced with ``Figure 1 (e)'', line 133 of the same page, ``Figure (d)''.
The phrase "shown in FIG. 1(d)" is corrected to "shown in FIG. 1(d)." (4) In the first line of page 7 of the specification box, the phrase "as shown in Figure (d)" is corrected to "as shown in Figure 1 (d)." (5) In the second line of page 8 of the specification, the phrase ``2-'' that says ``Figures (a) to (d)'' is corrected to ``Figure 1''. (6) Replace the drawing with the attached one. Agent: Patent Attorney Susumu Uchihara 3- 1.
Voluntary) 58.4.25 Yuu Ujo g8 1. Indication of the incident 1982 Patent Application No. 19923 2
, Title of the invention Method for manufacturing MO8 integrated circuit 3, Person making the amendment Relationship to the applicant's case 5-33-1 Shiba, Minato-ku, Tokyo (423
) NEC Corporation Representative Tadahiro Sekimoto (Contact address: NEC Corporation Patent Department) Detailed Description Column 6, Contents of Amendment (1) The claims are amended as shown in the attached sheet. (2) Grow one insulating film on page 2, line 10 of the specification.
The statement has been corrected to "grow a gate insulating film." (3) Delete the following from lines 10 to 11 on page 2 of the specification: ``A region of the insulating film to be made a direct contact is etched.'' (4) [In order to diffuse] on page 3, line 11 of the specification
Insert "Threshold voltage of the transistor; in addition to the inconvenience of fluctuation, direct contact i! If included" is inserted after. (5) On page 4, line 17 of the specification, after “is.”
In addition, in the latter method, it is also possible to pattern the polycrystalline silicon film 1-, form a high-melting point metal layer, perform heat treatment, and then remove the unreacted high-melting point metal. , the silicide is formed protruding from the patterned polycrystalline silicon, making it unsuitable for forming fine electrodes. ” is inserted. (6) "An insulating film on one main surface of a semiconductor substrate of the first conductivity type" in the second line of page 5 of the specification is corrected to "a gate insulating film on one main surface of a silicon semiconductor substrate." (7) Delete "After forming a desired opening in the insulating film" in the third line of page 5 of the specification. (8) From the fourth line to the fifth line of page 5 of the specification, the phrase "a second conductivity type impurity was doped on one main surface of the semiconductor substrate" was replaced with "on the gate insulating film". to correct. (9) Delete "direct contact and" on page 5, line 6 of the specification. (10) Delete ``1 hereby'' from lines 7 to 8 of page 5 of the specification. (11) From page 5, line 9 to line 13 of the specification, the phrase ``after implanting an impurity exhibiting a good second conductivity type from the upper surface of the layer'' is replaced by After ion implantation is performed from the upper surface of the silicon film to mix the high melting point metal and the silicon film. (12) "Hereinafter, regarding a typical embodiment of the present invention" on page 5, line 15 of the specification was changed to "Hereinafter, as an embodiment of the present invention, manufacturing a polycide gate including a direct contact." Correct the example to ``. (13) On page 7, line 14 and line 15 of the specification, there is a line that states, ``Although the above embodiments have shown a polycide gate including a direct contact, It is obvious that the present invention can also be applied to (Issue: In the 9th line of page 7 of the specification, the phrase ``impurities such as P+ and B+'' is corrected to ``n-type impurities such as P+ or non-impurity ions such as Si.'' (15) Specification After "There was" in the 20th line of page 7 [Furthermore, when polycrystalline silicon doped with boron is used, only Si or a combination of boron and silicon is used as the implanted ions. It was also very effective in this case. Insert -. Agent: Shinbetsu Uchihara, Patent Attorney The paper was etched leaving the area that should be claimed, and a high melting point metal layer was formed on the entire surface, and the layer was After performing ion implantation from the upper surface to mix the high melting point metal layer and the silicon film,
A heat treatment is performed at 00 to 600°C, and then the unreacted high melting point metal is etched to form a high melting point metal silicide layer on the silicon film surface in a self-aligned manner, followed by etching in a non-reducing gas atmosphere. A method for manufacturing an MO8 integrated circuit, characterized by performing heat treatment at 800°C or higher. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims]! After growing an insulating film on one main surface of the semiconductor substrate of the first conductivity type and providing a desired opening in the insulating film. A silicon film doped with a second conductivity type impurity is formed on one main surface of the semiconductor substrate, and the silicon film is etched through an etching tube, leaving areas to be used as direct contacts, gate electrodes, and interconnections, and etched onto the entire surface or the silicon film. A high melting point metal layer is formed only on the surface of the film, and from the top surface of the layer,
mixing the high melting point metal layer and the silicon film, and
A method for manufacturing an MO5 integrated circuit, which comprises implanting an impurity exhibiting a second conductivity type under conditions that allow the impurity to reach the surface of a semiconductor substrate in regions that will later become source and drain electrodes, and then performing heat treatment at about 600° C. or higher.