JPS58158942A - Semiconductor ic device and manufacture thereof - Google Patents

Semiconductor ic device and manufacture thereof

Info

Publication number
JPS58158942A
JPS58158942A JP4080582A JP4080582A JPS58158942A JP S58158942 A JPS58158942 A JP S58158942A JP 4080582 A JP4080582 A JP 4080582A JP 4080582 A JP4080582 A JP 4080582A JP S58158942 A JPS58158942 A JP S58158942A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
layer
withstand voltage
gt
lt
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4080582A
Inventor
Akira Muramatsu
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Abstract

PURPOSE:To obtain an IC with sufficient withstand voltage at high integration by a method wherein Si substrate is provided with LOCOS type and isoplanar type oxide film. CONSTITUTION:A dual mask of SiO2 and Si3N4 is formed on N epitaxial layer on P<-> type substrate wherein N<+> layer is embedded and resist mask 9 is provided to form a convex 10 in bipolar element region II required of high withstand voltage. When the mask 9 is removed to form an oxide film for separation, a layer 5b reaches embedded layer while another layer 5a does not. Another resist mask 11 is provided to form P<-> layer 12, P<+> layer and CMOSFET separated by LOCOS type oxide film is formed on the further regionI. The high integration may be sustained since a channel stopper is not required under separated layer due to needless high withstand voltage. On the other hand, the bipolar elements separated by isoplanar type oxide film is formed in the region II required of high withstand voltage, however, the separated layer reaching substrate being formed, the withstand voltage is sufficient without channel stopper at all. Through this combined system, the chip size may be reduced remarkably.
JP4080582A 1982-03-17 1982-03-17 Semiconductor ic device and manufacture thereof Pending JPS58158942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4080582A JPS58158942A (en) 1982-03-17 1982-03-17 Semiconductor ic device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4080582A JPS58158942A (en) 1982-03-17 1982-03-17 Semiconductor ic device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS58158942A true true JPS58158942A (en) 1983-09-21

Family

ID=12590850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4080582A Pending JPS58158942A (en) 1982-03-17 1982-03-17 Semiconductor ic device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS58158942A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226892A2 (en) * 1985-12-17 1987-07-01 Siemens Aktiengesellschaft Process for manufacturing of bipolar and complementary MOS-transistors on a common silicon substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137482A (en) * 1974-04-18 1975-10-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137482A (en) * 1974-04-18 1975-10-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226892A2 (en) * 1985-12-17 1987-07-01 Siemens Aktiengesellschaft Process for manufacturing of bipolar and complementary MOS-transistors on a common silicon substrate

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