JPS58158942A - Semiconductor ic device and manufacture thereof - Google Patents
Semiconductor ic device and manufacture thereofInfo
- Publication number
- JPS58158942A JPS58158942A JP4080582A JP4080582A JPS58158942A JP S58158942 A JPS58158942 A JP S58158942A JP 4080582 A JP4080582 A JP 4080582A JP 4080582 A JP4080582 A JP 4080582A JP S58158942 A JPS58158942 A JP S58158942A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- oxide film
- mask
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000007127 saponification reaction Methods 0.000 claims 1
- 230000002195 synergetic effect Effects 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 230000002459 sustained effect Effects 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明ａ牛４体集棟回路装置（以下ＩＯと略称する）Ｋ
胸する。[Detailed description of the invention] The present invention a cow 4-body integrated circuit device (hereinafter abbreviated as IO) K
Chest.
一つの半婆体基体上にバイポーラ集子を含む回路とＭＯ
８集子ＩＩ−ｔむ回路とｔ共存さぜる工ＣＶこおいて、
谷諏子や１ｇ１Ｎ１関ｔ［気的に分陰（アイソレーショ
ン）するために半導体ＰＮ接合を利用するブレーナ方式
１遇択酸化により半導体表面に形成した半導体酸化膜ｔ
オリ用するＬＯ００８方式がそれぞれ単独に採用はれて
ｂる。このうちプレーナ方式は、例えば第１図に示す↓
うに、Ｐ−型基板１上にＮ 埋込ｌ曽２１エビｌキシャ
ルＮ層３葡形成し、Ｎ鳩３我面からＰ−基板ＩＫ接続す
るアインレーションＰ／ｍｌニー拡散するものであるか
、アイソレーションＰ盾番自体が倒方間に拡散ｌ槓を広
くとり、耐圧ｔ＊ぶされるバイポーラ素子７タ離する場
曾Ｎ層内に形成されるコレツ４やペースとの関−を充分
にとらなければならず集積度が低い。一方； ＬＯＯＯ
Ｅ１方式は、第２図にボ丁ように、エピタキシャルＮ層
３の表面ｋｌ［（ヒ性マスクを用いて選択的に歌化して
廖い毅化課５【形成するものでおり、バイポーラ本子七
分離する場合、分離子Ａ地分にＢ（ボロン）イオン打込
みにより酸化−５の直下及び周辺に分庫用Ｐ＃ｔｉｋ設
ける必要があり、この場合も２層６の几めの月参ぜ余裕
が必賢で集積度【大きくすることができない。Circuit containing bipolar collector and MO on one semi-circular substrate
8 Collection II-T circuit and t coexistence engineering CV,
Suzuko Tani and 1g1N1 [semiconductor oxide film formed on the semiconductor surface by selective oxidation using Brehner method 1 selective oxidation using semiconductor PN junction for atmospheric isolation.
Each of the LO008 methods used for this purpose is independently adopted. Among these, the planar method is shown in Figure 1, for example↓
Is it possible to form an N buried layer 21 and an axial N layer 3 on the P-type substrate 1, and to connect the P-type substrate IK from the N layer 3 side by diffusing the insulation layer P/ml knee? The isolation P shield itself has a wide diffusion layer between the two sides, and the relationship between the bipolar element 7 which is exposed to the withstand voltage t* and the distance formed in the N layer and the pace is sufficiently taken. Therefore, the degree of integration is low. On the other hand; LOOO
In the E1 method, as shown in Fig. 2, the surface of the epitaxial N layer 3 is formed by selectively converting it into a bipolar layer using a polarizing mask. In the case of separation, it is necessary to install P#tik for a separate storage immediately under and around the oxidation-5 by implanting B (boron) ions into the separator A region, and in this case, there is also a small monthly separation margin of 2 layers 6. is wise and the degree of integration [cannot be increased].
分蘭方式としてはこれ以外に半導体表面に形成した凹部
上酸化し基板に違する深い酸化ｆｌｔ利用するアイソプ
レーナ方式がある。しかしこの方式による深い酸化膜は
ＭＯ８案子Ｑ９離には必要でないため、専らパイボーラ
エＣにお灯る分離に利用さ庇ている。In addition to this, there is an isoplanar method that uses deep oxidation flt, which oxidizes the recesses formed on the semiconductor surface and differs from the substrate. However, the deep oxide film created by this method is not necessary for the separation of MO8 and Q9, so it is used exclusively for the separation of Pyborae C.
本発明はバイポーラＭＯ８工Ｃに関しては従来併用され
なかったＬＯＯＯ８とアイソプレーナ技術ｒ一つの基板
上に適用することにより、集ａ度を篩め、しかも充分な
耐圧ｋ１Ｍ持でさる半導体装置ｒ提供することｒ目的と
する。The present invention provides a semiconductor device r with reduced aggregation and sufficient withstand voltage k1M by applying LOOO8 and isoplanar technology, which have not been used together in the past, on a single substrate for bipolar MO8 technology. This is the purpose.
５１！３図（ａ） 〜（ｆ）ｉｆ Ｐ −ｍ ８１ 、
！板上にＮＰＮ）ランジスタと相葡形ＭＯ８Ｆ１１ｉＴ
ｋ形敗する場曾に本発明ｒ適用した冥塵ガプロセスｉ示
し、以−Ｆ各１ａｉ［便って峰述丁ゐユ
（ａ） Ｐ−型８１基板ｌの表面にドナ不純物（８ｂ
又はＡθ）【部分拡散してＮ＋埋込層２を形＆Ｌ７、七
〇上ＶＣｋＪ’１ＪＢＬ層３ｋ１．５〜２．５μｍの犀
さＶＣエピタキシャル成長させる。このＭ一層３の表面
に薄す酸化膜（ＳｉＯｇｌＭり７１１”介して耐酸化性
膜としてナイトライド（ｓｉｓＮａ）膜８を形成する。51!3 Figures (a) to (f) if P-m 81,
! NPN) transistor on the board and MO8F11iT
The present invention is applied to the Meijin gas process I in the case where the P-type 81 substrate is destroyed.
or Aθ) [Partially diffused to form an N+ buried layer 2 with a shape &L7, 70, and VCkJ'1JBL layer 3k with a thickness of 1.5 to 2.5 μm and VC epitaxially grown. A nitride (sisNa) film 8 is formed as an oxidation-resistant film on the surface of this M layer 3 via a thin oxide film (SiOglM layer 711'').
（１）） 分離用酸化ｍｔ−形成すべき部分のナイト
ライド１Ｆ一部分的に除去する。この後、ＭＯ８３１子
を形成すべき領域（１）上勿ホトレジスト・マスク９で
傍い、バイポーラ素子を形成丁べき領域（ＩＩ）の紡紀
ナイトライドを除去した部分のＳ１層３ｔエツチして深
さＬｐｍ程度の凹部１０會形成する。(1)) Partially remove nitride 1F in the part to be formed of oxidized mt for separation. After this, of course, a photoresist mask 9 is placed over the area (1) where the MO831 element is to be formed, and the S1 layer 3t is etched deeply in the area (II) where the bipolar element is to be formed, where the spiny nitride has been removed. 10 recesses with a length of about Lpm are formed.
（０） ホトレジスト・マスク９に＊り除き、酸化処
理を行なうことによシナイトライド除去部のＳ１層に適
訳的に分離用酸化１１１−形成する、この分隘用鹸化膜
の廖さＨｌ、５μｍ１Ｍ度でおり、−域■では分離用酸
化１１５ａにＮ 埋込１＃Ｉ２やＰ−基＆ｌに運するこ
とがないが、領域…では凹ｓｌＯに勢威され九分離用版
化膜５ｂはＮ 坤込層２やＰ−基板ＩＫ帰絖される。(0) The thickness of the saponified separation film 111, which is appropriately formed on the S1 layer of the cinitride-removed portion by removing it on the photoresist mask 9 and performing oxidation treatment, 5μm and 1M degree, and in the − region ■, the isolation oxide 115a does not carry N to the embedded 1#I2 or the P− group &l, but in the region..., it is dominated by the concave slO, and the isolation plated film 5b carries N. The embedded layer 2 and the P-substrate IK are applied.
（（Ｌ） ナイトライドｌ１ｌｉ８に取り除さ、表面
の一部ｒホトレジストマスク１１で轡って分Ｉ＠亀骸化
良でセルアラインした状態でＢ（ボロン）不純物ｔイオ
ン打込み、砿散し、ｉｉＩ域Ｉにおいてｔ濃度のＰ−ウ
ェル１２を形成する。他方領域１１においてはベース形
成のためそれより高一度のＰ 層１３【形成する。((L) Removed with nitride l1li8, covered part of the surface with a photoresist mask 11, aligned the cell with a part I@Kamekukaryo, implanted B (boron) impurity t ions, scattered, iiiI In region I, a P-well 12 with a t concentration is formed.On the other hand, in region 11, a P-well 13 with a higher concentration is formed to form a base.
（６）１ｍｌ＃Ｉにおいて表面の一部に薄い熱酸比換１
４を介してポリ８１又はＭＯ等による絶縁ゲー）１５を
形成し、これら絶縁ゲート１５と分離用酸化−５ａｒ（
よりセルファラインされたＮ 拡散ソース・ドレイン１
６及びＰ 拡散ソース・ドレイン１７會形成する。(6) In 1ml #I, a thin layer of hot acid 1 on a part of the surface
An insulating gate 15 made of poly 81 or MO or the like is formed through the insulating gate 15 and an oxidized -5ar(
More self-aligned N diffused source/drain 1
6 and P diffusion sources/drains 17 are formed.
一方、領域ｎにおいて一１１ｓｋＭ酸化１１１１１８で
マスクしてＮ＋拡散工ξツタ１９に一形成するとともに
分離用酸化ｇｓｂでセルファラインされたＮ＋ＢＨコレ
クタコンタクト部２０１１−形成する。同図（ｆ）ｔ！
この工１１における各拡散層の平面的配ａｔ示すもので
ある。On the other hand, in region n, an N+ diffusion layer 19 is formed by masking with 111skM oxide 111118, and an N+BH collector contact portion 2011 is self-lined with isolation oxide GSB. Same figure (f) t!
The planar arrangement of each diffusion layer in this process 11 is shown.
この後、○ｖｐ（化学気相析出）法によるＰａ（）（リ
ンシリケート・ガラス）ａ１２１に形成し、コンタクト
ホトエッチ後にムｚ；ｉ１ｍ、ムｌのパターニングニッ
チを行なうことにより、各領域の素子の％他関を相互Ｋ
１１ｉｌｌするムｌ配８２２に形成丁る。。After this, elements in each area are formed on Pa() (phosphosilicate glass) a121 by ○vp (chemical vapor deposition) method, and patterning niches of muz; i1m and mu1 are performed after contact photoetching. % of other companies mutually K
11 illumination pattern 822 is formed. .
同図において、領域！簡にはＮチャネルＭＯ８ＦＩＴ及
びＰチャネルＭ Ｏ８Ｐ ｌｃ ？ ＃構Ｗｉｉ、すｆ
Ｌｈとともに、領域１１１１１に：はバイポーラＭＰＮ
）ランジスタが構成されるユ
以上ｖｌ施例で述べた本発明によ、７′Ｌは下記の効果
が奏せられる。In the same figure, area! Simply put, N channel MO8FIT and P channel MO8P lc? # Structure Wii, Suf
Along with Lh, in region 11111: is bipolar MPN
) According to the present invention described in the above embodiments, the transistor 7'L has the following effects.
（１） ＊域１ｌｌａはＬＯＯＯＢ方式ノ酸化ａｌｌ
Ｋ！、！！７分騰された相補的ＭＯ８回路か形成される
。このＭＯ８回路においては耐沿ｔ−誉しないがら分離
用酸化換の下−や周辺においてＰ多分離層６を設ける必
ｌ！かなく、シ友がってこの部分での集積ＦＩＩＬ′＋
ｒ：元分に大きく大きく保つことができる。(1) *Area 1lla is LOOOB method oxidation all
K! ,! ! A complementary MO8 circuit with a 7 minute increase is formed. In this MO8 circuit, it is necessary to provide a P isolation layer 6 under and around the oxidation layer for isolation, although it is not recommended for corrosion resistance. Without further ado, our friends are accumulating FIIL'+ in this part.
r: It is possible to keep the original amount large.
（２） 領域ｌ−はアイソプレーナ方式の酸化によｐ
分離され九バイポーラ（ロ）路が形成される。このバイ
ポーラ回路では耐圧【費するが、分−用酸化候が凹部に
よシＮ層円に深く形成されＰ−基板に接続するためＰ型
分庫層を設けなくとも耐圧が侍られ、したがってこの部
分での集積ｆは小さくならない。(2) Region l− is p due to isoplanar oxidation.
They are separated to form nine bipolar (b) tracts. In this bipolar circuit, the withstand voltage [is required], but since the dividing oxidation is formed deep in the N-layer circle through the recess and connected to the P-type substrate, the withstand voltage can be met without providing a P-type dividing layer. The accumulation f at a portion does not become small.
上記（１）（２）↓９、本発明によればプレーナ方式の
みの場合に比してバイポーラ回路の面積を約５０％、Ｌ
ＯＯＯＢ方式のみの場合に比して約２０Ｘ縮小し、全体
としてチップサイズを大幅に―小することができる。According to the above (1) (2) ↓9, according to the present invention, the area of the bipolar circuit can be reduced by approximately 50% compared to the case of only the planar method.
The size is reduced by about 20X compared to the case of using only the OOOB method, and the overall chip size can be significantly reduced.
本発明は前記状Ｊ１例に限定されず、これ以外の撞々な
形での実施が可能であるが、％ＫＮＰＮ）ランジスタで
耐圧１５ｖ以下のバイポーラＭＯ８ＩＣの全てに通用し
て奪効である。The present invention is not limited to the above-mentioned example J1, and can be implemented in various other forms, but it is applicable and effective to all bipolar MO8ICs that are %KNPN) transistors and have a withstand voltage of 15V or less.
８１図及び１ｇ２図は在来の分離方式を示す半導体素子
の一５ＩＩＦｒｒｊＩＪ図である。＠３図−） 〜（ｆ
）＃：を本発８１：ｌＶこよる半導体集積回路ｉ！皺の
製造プロセスの各工程を示し、このうち（ａ） 〜（＠
）＄１！ｌ１ｒｌ１図、（ｆ）Ｈ（ｅ）に対応する平面
図、第４図は第３図のプロセスを経て完成した半尋体集
槓回路装置の断面図である。
ｌ・・・Ｐ−基板、２・・・Ｍ＋涯込層、３・・・エピ
タキシャルへ、４・・・アイフレー９１フ２層、５・・
・分１１川緻化換、６・・・９庫用Ｐ層、７・・・薄い
酸化膜、８・・・ナイトライド−１９・・・ホトレジス
ト・マスク、１０・・・凹部、１１・・・ホトレジスト
マスク、１２・・・Ｐ−ウェル、１３・・・Ｐ ペース
、１４・・・熟酸化映、１５・・・ゲート、１６．１７
・・・ソース・ドレイン、１８・・・熱酸化編、１９・
・・工ｉ７４．２０・・・コレクタコンタクト、２１・
・・Ｐ８ＧＩｍ、２２・・・ムｌ配−３第 １ 図
第 ２ 図81 and 1g2 are diagrams of a semiconductor device showing a conventional separation method. @Figure 3-) ~(f
) #: The original 81: Semiconductor integrated circuit due to lV i! Each step of the wrinkle manufacturing process is shown, among which (a) ~ (@
) $1! FIG. 4 is a cross-sectional view of the half-body integrated circuit device completed through the process shown in FIG. 3. l...P-substrate, 2...M+ layer, 3...to epitaxial layer, 4... Eye-Fray 91 2nd layer, 5...
・Minute 11 river densification conversion, 6...9 P layer for storage, 7...thin oxide film, 8...nitride-19...photoresist mask, 10...concavity, 11...・Photoresist mask, 12...P-well, 13...P pace, 14...ripe oxide film, 15...gate, 16.17
...Source/drain, 18...Thermal oxidation, 19.
...Eng.i74.20...Collector contact, 21.
...P8GIm, 22...Ml-3 Figure 1 Figure 2
Claims (1)
ｔされ、この半導体層はその表面に選択的に形成さｆＬ
７を辱い半導体酸化ｍによって第ｌの回路を肩する１７
４＠域群と′ｍ２の回路を有する島憤域群とに分離され
、第１の（ロ）略を刹する島憤域に上記半導体層表面か
ら基体に運する酸化膜によって分離されるとともに第２
の回路を有する島憤域は基体に遜することのない酸化１
ｉ＠ｌ［よって分離されている仁とＩＩ−特徴とする半
導体集軸回路装置。 ２、第１ （ＤＩＦＩ１１！ｉ％はバイポーラ素子を言
む回路であり、＃！２の回ｗ１はＭＯ８素子【言む回路
でめる特ト饋求の範曲絡１墳に記載の半導体集軸回路装
置。 ３、第１４篭ｍ８１半尋俸Ａ−板の一正面上に第２専畦
型＾磯度埋込層を弁して第２纒嵐番は磯鼓半尋体層ケ成
長路ぜる工程、纂２尋電型低一度千導体層表面に耐酸化
性マスクを部分的に彫戚する１機、耐鹸化性マスクで機
った一Ｓ領域上りｄのマスクで慢い、他部の耐酸イと性
マスクで橿われない半導体層表面−會エッチして凹部を
形成する工程、第２のマスクｋｍ除いて耐酸化性マスク
で柵わｎない部分で凹部の形成された半導体部分に基板
に運する酸化膜を形成するとともに凹部の形成されない
半導体部分表面に酸化ａｒ形成する工程、基板に達する
酸化−で曲管れた半導体領域に上記酸イヒ膜ｔマスクの
一部として不純物會目己督合的に拡散してバイポーラ素
子を構成する各領域を形成し、他方、基＆に通しない酸
化膜で囲まれた半導体ｉｉｉ域の一部にＩＰ縁ケート勿
形成し絶縁ゲートと１に酸化膜ｔマスクとして自己誓合
的にＭＯ８素イｋｌｌＪｇするンース・ドレインを形成
することｔ舟倣とする半導体集軸回路装置の製造法。[Claims] 1. Semiconductor layers of different conductivity types are formed on the living body substrate.
t, and this semiconductor layer is selectively formed on its surface fL
7 and shoulder the lth circuit by semiconductor oxidation m17
It is separated into the 4@ region group and the island region group having a circuit of 'm2, and the first (b) region is separated by an oxide film carried from the surface of the semiconductor layer to the substrate. Second
The island region has a circuit of oxidation 1 that is comparable to the substrate.
A semiconductor integrated circuit device characterized by i@l and II separated by i@l. 2, 1st (DIFI11!i% is a circuit that refers to a bipolar element, and #!2's w1 is a semiconductor collection described in Tokuto Hokyo's Hankyokuro 1 tomb with a circuit that refers to MO8 element. Axial circuit device. 3. On one front of the 14th basket m81 half-fatty layer A-board, the second dedicated furrow type ^ Isodo buried layer is opened, and the second wire arashi is grown by Isozumi half-fatty layer. In the wiring process, an oxidation-resistant mask is partially carved on the surface of the 2-layer conductor layer, and a saponification-resistant mask is used to create a mask with an S area up to d. The surface of the semiconductor layer that is not covered by the oxidation-resistant mask in other parts - the process of etching to form a recess, the semiconductor with the recess formed in the part that is not covered by the oxidation-resistant mask except for the second mask km A process of forming an oxide film to be carried to the substrate and forming an oxide film on the surface of the semiconductor part where no recess is formed, and adding an impurity as part of the oxide film t mask to the curved semiconductor region due to the oxidation that reaches the substrate. Each region constituting the bipolar element is formed by diffusion in a synergistic manner, and an IP edge gate is formed in a part of the semiconductor region iii surrounded by the oxide film that does not pass through the base to form an insulating gate. 1. A method for manufacturing a semiconductor integrated circuit device, which includes forming a source drain that self-asserts MO8 element as an oxide film mask in step 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4080582A JPS58158942A (en) | 1982-03-17 | 1982-03-17 | Semiconductor ic device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4080582A JPS58158942A (en) | 1982-03-17 | 1982-03-17 | Semiconductor ic device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58158942A true JPS58158942A (en) | 1983-09-21 |
Family
ID=12590850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4080582A Pending JPS58158942A (en) | 1982-03-17 | 1982-03-17 | Semiconductor ic device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58158942A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0226892A2 (en) * | 1985-12-17 | 1987-07-01 | Siemens Aktiengesellschaft | Process for manufacturing of bipolar and complementary MOS-transistors on a common silicon substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50137482A (en) * | 1974-04-18 | 1975-10-31 |
-
1982
- 1982-03-17 JP JP4080582A patent/JPS58158942A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50137482A (en) * | 1974-04-18 | 1975-10-31 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0226892A2 (en) * | 1985-12-17 | 1987-07-01 | Siemens Aktiengesellschaft | Process for manufacturing of bipolar and complementary MOS-transistors on a common silicon substrate |
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