JPS5522888A - Manufacturing method of insulation gate type semiconductor device - Google Patents

Manufacturing method of insulation gate type semiconductor device

Info

Publication number
JPS5522888A
JPS5522888A JP10884478A JP10884478A JPS5522888A JP S5522888 A JPS5522888 A JP S5522888A JP 10884478 A JP10884478 A JP 10884478A JP 10884478 A JP10884478 A JP 10884478A JP S5522888 A JPS5522888 A JP S5522888A
Authority
JP
Japan
Prior art keywords
sio
type
laminated
selectively
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10884478A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP10884478A priority Critical patent/JPS5522888A/en
Publication of JPS5522888A publication Critical patent/JPS5522888A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain a MISFET device by a pn reverse bias separation by forming an n-type bury layer by utilizing for a mask a field oxidization layer buried selectively in a p-type Si substrate face.
CONSTITUTION: A field oxidization film is buried by a double mask of an Si3N4 and SiO2 on a p-type Si, and an n-type epitaxial-layer 3 is laminated to form a field oxidization film 23 similarly. Successively, an SiO26, Si3N47 and SiO28 are laminated. Next, a p+epitaxial 9 is laminated to be covered with Mo, and a gate 15, lead 11 and capacity portion 36 are selectively formed by etching. Successively, a thermal diffusion is provided from an opening to form p+layers 13 and 14. Next, an SiO216 is covered, and an opening is selectively provided to form an Al electrode 18. According to such a process, a pn reverse bias separation is formed to easily establish a formation of an LSI or IC. The source and drain utilize the lead commonly. A conventional electrode having many failures can be removed, the manufacture of a device be easily established, and the composite integration circuit be also freely formed.
COPYRIGHT: (C)1980,JPO&Japio
JP10884478A 1978-09-05 1978-09-05 Manufacturing method of insulation gate type semiconductor device Pending JPS5522888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10884478A JPS5522888A (en) 1978-09-05 1978-09-05 Manufacturing method of insulation gate type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10884478A JPS5522888A (en) 1978-09-05 1978-09-05 Manufacturing method of insulation gate type semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3062571A Division JPS5624385B1 (en) 1971-05-07 1971-05-07

Publications (1)

Publication Number Publication Date
JPS5522888A true JPS5522888A (en) 1980-02-18

Family

ID=14495005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10884478A Pending JPS5522888A (en) 1978-09-05 1978-09-05 Manufacturing method of insulation gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5522888A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2026209A7 (en) * 1968-12-16 1970-09-18 Fairchild Camera Instr Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2026209A7 (en) * 1968-12-16 1970-09-18 Fairchild Camera Instr Co

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