JPS63181365A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the process of manufacture as well as to contrive accomplishment of a shallow base coupling by a method wherein the emitter and the base lead-out region of a bipolar type transistor and the source and drain region of an MOS transistor are formed simultaneously. CONSTITUTION:A polycrystalline silicon is covered with a field oxide film 3 and an oxide film 6, and a gate part 4 of p-type and n-type MOS transistors, the emitter region of an n-p-n bipolar transistor, and the pattern 5 to be used for formation of a base electrode lead-out region are formed respectively. Then, ions are implanted using a resist pattern 7 and a gate electrode 4 as a mask, and after resist has been removed, an annealing operation is performed and a source and drain region 8', a collector electrode lead-out region 9', and an emitter region 10' are formed. Then, ions are implanted using a resist pattern 7' and the gate electrode 4 as a mask, and after the resist has been removed, an annealing operation is performed, a source and drain region 12' and a base electrode lead-out region 13' are formed. Subsequently, a resist pattern 7'' is formed, the polysilicon layer 5 used as a mask is removed using said resist pattern 7'' as a mask, ions are implanted, and after the resist has been removed, an annealing operation is performed, and a base region 15' is formed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device useful for LSI etc., and particularly to a Bi-MOS type semiconductor having a MOS type semiconductor device and a bipolar type semiconductor device on the same semiconductor substrate. The present invention relates to a method for manufacturing a device.

[Conventional technology]

In recent years, MO3 type transistors and other MO3 type transistors, which are relatively easy to integrate, have been used as active elements in semiconductor integrated circuit devices such as LSIs.
Not only type 3 semiconductor devices but also bipolar type semiconductor devices such as bipolar type transistors, which can be operated at higher speeds, are often used. In particular, a semiconductor device in which a MOS type semiconductor device and a bipolar type semiconductor device are formed on the same semiconductor substrate (hereinafter referred to as a Bi-MO3 type semiconductor device) has the advantages of low power consumption of the MO3 type semiconductor device and the advantages of the bipolar type semiconductor device. It is attracting attention as a high-performance semiconductor device that has the advantage of high current drive capability.

Although the manufacturing method is complicated with many manufacturing steps, MO3
In cases where the region forming process for a type semiconductor device and that for a bipolar type semiconductor device can be used, the regions are formed simultaneously in parallel to increase the degree of integration without increasing the number of steps. An example of this is shown in Figure 2 as an n-type MOS transistor (n-p-n).
A case where transistors are formed on the same substrate will be described.

(1) After forming the n+ type buried layer 22 in the p-type silicon substrate 21, the n-type epitaxial layer 2 with a thickness of 2 μm is formed.
After growing 3, boron (B) is implanted and diffused into the p-type well region 24 and the p-type isolation region 25 to form the respective regions (FIG. 2(a)).

(2) Next, after forming a field silicon oxide film 26 by, for example, selective oxidation (LOGO3) method, boron (B) ions are implanted into a part of the n-type region that is to become a base region to form a base region 28. At the same time, a gate oxide film 27 is also formed (FIG. 2(b)).

(3) After forming the n3 type collector extraction region 29 and the n' type emitter region 30 by implanting arsenic (As) ions by selective ion implantation, the first connection layer 31 is connected to the n-pn type transistor part and the MO3 type. A transistor portion is formed at the same time (FIG. 2(C)).

(4) After forming the n" type source and drain regions 32 by ion implantation, the p type base extraction region 33 is formed (at this time, if necessary, the source and drain regions of the p type channel MoS transistor are also formed. (can be formed at the same time)
(Figure 2(d)).

(5) Cover the surface of the semiconductor substrate including the first connection layer 31 with a silicon oxide film 34 as a glabellar insulating film (Fig. 2(e)
)).

(6) Form connection holes to each region to form the second connection layer 3
5 to complete the circuit (Fig. 2(f)).

As mentioned above, the conventional bipolar transistor manufacturing process includes several mask steps, namely, p-type well formation, n-type channel MOS transistor source and drain region formation, p-type channel MOS transistor source,
A B1-CMOS transistor can be formed on the same semiconductor substrate by simply adding drain region formation, etc. (
For example, IHBE Transaction on El
ectron Devices Vol, HD-32
, No. 2, Feb, 1985 p232-236 or Deges to Technical Pap
ers of IEDM '85 p423-426
reference).

[Problem that the invention seeks to solve]

In order to increase the operating speed of a bipolar transistor, the depth of the base region should be increased, the emitter, the minimum distance between the pn junction between the base regions and the pn junction between the base and collector regions,
It is necessary to form d) in FIG. 1(g) shallowly. Therefore, it is necessary to perform the heat treatment process after forming the base region at a lower temperature and for a shorter time, and to reduce the number of times as much as possible. this is,
This is because boron (B) ions, which are generally implanted when forming the base region, have a large diffusion coefficient and a property that the diffusion region expands each time heat treatment is performed.

However, in a bipolar transistor, a collector region is usually formed first in a semiconductor substrate, then a base region and an emitter region are formed in this order, so heat treatment for forming the emitter region after the base region is formed cannot be avoided.

In addition, when manufacturing a Bi-MO3 type semiconductor device, the second
As shown in the figure, after the base region is formed, heat treatment is additionally performed during the gate electrode formation and the source and drain region formation, resulting in at least two additional heat treatments, and these heat treatments increase the depth of the junction. There was a problem.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a manufacturing method that simplifies the manufacturing process of a Bi-MO3 type semiconductor device as much as possible, and that also realizes a shallower base junction of a bipolar transistor.

[Means and effects for solving the problem] Therefore, in the present invention, in the manufacturing method of a Bi-MO3 type semiconductor device, masking for forming the emitter region and base electrode extraction region of the bipolar transistor and the gate electrode of the MOs transistor are performed. - Simultaneously forming the source and drain regions of the MOS transistor, the emitter region of the bipolar transistor, and the base electrode extraction region using this pattern as a mask; the emitter region and the base electrode of the bipolar transistor; This method is characterized in that the base region is formed after the drawer region is formed.

Formation of emitter region and base electrode extraction region
The manufacturing process can be simplified by forming the source and drain regions of the S transistor at the same time, and the heat treatment process after forming the base region can be shortened by forming the base region after forming the emitter region and base electrode extraction region. However, a predetermined shallow base junction can be realized.

〔Example〕

An embodiment of the invention will be described with reference to FIG.

FIG. 1 is a cross-sectional view of the manufacturing process for manufacturing an npn-type bipolar transistor, p-channel, and n-channel CMO5MOS transistors on a silicon substrate.

(1) A relatively deep n-type diffusion layer 2 (hereinafter referred to as n-well) with a junction depth of about several μm is formed on a p-type silicon substrate 1. This is done by a conventional method such as selectively implanting n-type impurities, such as phosphorus (P) ions, into a p-type silicon substrate and performing heat treatment.

Next, by forming a field oxide film 3 by selective oxidation (LOGO3) method, a p-type MO3) transistor, an n
After separating each region of the transistor (type MOS) transistor and the npn bipolar transistor and heating it in an oxidizing atmosphere to form a gate oxide film 6, a film of polycrystalline silicon doped with phosphorus is deposited and patterned. , the gate portion 4 of the n-type MOS transistor, the emitter region of the npn bipolar transistor, and the pattern 5 for forming the base electrode extraction region are formed by patterning at the same time (FIG. 1(a)).

(2) Next, a photoresist film is deposited using photolithography, and then patterned to form a resist pattern 7, leaving the n-type MOS transistor portion 8, the collector electrode extraction formation region 9, and the emitter formation region 10. 4 as a mask, use an n-type impurity such as arsenic (As).
) Ions are implanted to introduce high concentration n-type impurities into each region (FIG. 1(b)).

(3) After that, the resist pattern 7 is removed and a heat treatment called annealing is performed to remove the source, drain region 8', collector electrode extraction region 9', and emitter of the n-type MOS (n-type MOS) transistor consisting of an n-type high concentration impurity diffusion layer. Area 1
0' is formed at the same time.

Next, after depositing a photoresist film using photolithography technology,
A resist pattern 7' is formed leaving the p-type MO3I-transistor portion 12 and the base electrode extraction forming region 13,
Using this and the gate electrode 4 as a mask, p-type impurities such as boron (B) ions are implanted to introduce high-concentration p-type impurities into each region (FIG. 1(C)).

(4) After this, the resist pattern 7' is removed and annealing is performed to form a p-type MO consisting of a p-type high concentration impurity diffusion layer.
3) Form the source and drain regions 12' and base electrode extension region 13' of the transistor.

Next, a photoresist is applied again by photolithography and patterned to form a resist pattern 7'' leaving the base formation region 15 of the npn transistor. Using this as a mask, dry etching or wet etching is performed to form a resist pattern 7'' on the base formation region 15. The polycrystalline silicon layer 5 doped with is removed (Fig. 1(d) 'I
.

(5) Then, using the resist pattern 7'' as a mask, boron (B) ions, which are p-type impurities, are implanted to introduce the p-type impurity into the base formation region (FIG. 1(e)).

In this case, the concentration and amount of boron ions can be selected under optimal conditions for forming the base region.

(6) After removing the resist pattern 7#, annealing is performed to form the base region 15' of the npn transistor. After forming the base region, for example, a silicon oxide film or a PSG (phosphorus glass) film 17 is deposited as an interlayer insulating film by CVD.
After the film is deposited, it is flattened using a method or the like (FIG. 1(f)).

(7) Finally, a contact hole is opened in the glabella insulating film 17, and the extraction electrode 18 is deposited and patterned by sputtering, for example, aluminum (CAl), to complete the circuit (FIG. 1(g)).

Although this embodiment describes an example in which phosphorus-doped polycrystalline silicon is used as the gate electrode material, the present invention is not limited to this. For example, titanium (Ti) or tungsten may be used if the same effect can be obtained. It is also possible to use high melting point metals such as (W), a laminated structure of these metals and polysilicon, or silicides of these metals.

Further, in this embodiment, heat treatment (annealing) after impurity ion implantation is performed after each impurity ion implantation step, but this can also be performed after the final ion implantation step.

Furthermore, this embodiment uses an n-type MO3) transistor, a p-type MO3) transistor, and a p-type MO3) transistor.
Although an example in which an S transistor and an NPN bipolar transistor are formed in one silicon substrate has been described, the present invention is not limited to this, and of course any combination is possible as long as it is a Bi-MO3 type semiconductor device. It is.

〔Effect of the invention〕

According to the present invention, only one layer is added to the photopattern required for the manufacturing process of a normal MO3 type semiconductor device, that is, as shown in FIG.
d) A Bi-MO3 type semiconductor device can be manufactured by simply adding the photoresist pattern 7'' necessary for creating the base forming region 15 in (e), and the increase and complexity of the process can be kept to a minimum. was completed.

Furthermore, by performing the step of forming the base region of the bipolar transistor after forming the emitter region, it is possible to reduce the temperature and shorten the heat treatment step after forming the base region.

Therefore, its depth is the thickness d) of the base region in Figure 1 (g).
This makes it possible to realize shallower base junctions on the order of submicrons, making it possible to obtain high-performance bipolar transistors with high operating speeds.

[Brief explanation of the drawing]

FIG. 1 is a process explanatory diagram of an embodiment of the present invention, and FIG. 2 is a process explanatory diagram of a conventional example. 1...p-type silicon substrate 2-n-type well region 3
-・Field oxide film 4-・Gate electrode 5-Mask pattern 6-・Gate oxide film 7.7', 7#-・
- Photoresist 8', 12' - Source, drain region 9' - Collector electrode extension formation region 10 - Emitter formation region 13 - Base electrode extension formation region 15' - Base region 17... Interlayer insulating film 18- Extraction electrode patent applicant Fuji Xerox Co., Ltd. Representative patent attorney Akira Yamatani Sakae 1 (So/)/) PMO8NM (MNPN) 5>Vj,! Tranff; da transition (da 1st figure (zono 2) 2nd figure (sof)/)

Claims (3)

[Claims] (1) In a method of manufacturing a semiconductor device in which a bipolar type semiconductor device and a MOS type semiconductor device are formed on the same semiconductor substrate, an electrode material that will become the gate electrode of the MOS type semiconductor device is patterned, and this is used as a mask to form the MOS type semiconductor device. A step of forming a source and drain region of a bipolar semiconductor device and a step of forming an emitter region or a base electrode lead-out region of a bipolar semiconductor device are performed simultaneously, and the base region of the bipolar semiconductor device is formed after both steps are completed. A method for manufacturing a semiconductor device. (2) Before forming the base region of the bipolar semiconductor device, ion implantation into the base region is performed after removing the patterned gate electrode material used in forming the emitter region and the base electrode extraction region. A method for manufacturing a semiconductor device according to claim 1, characterized in that: (3) A method for manufacturing a semiconductor device according to claim 1, characterized in that a complementary semiconductor device is formed as the MOS semiconductor device.