JPS5815252A - Bump structure - Google Patents
Bump structureInfo
- Publication number
- JPS5815252A JPS5815252A JP56112142A JP11214281A JPS5815252A JP S5815252 A JPS5815252 A JP S5815252A JP 56112142 A JP56112142 A JP 56112142A JP 11214281 A JP11214281 A JP 11214281A JP S5815252 A JPS5815252 A JP S5815252A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bump
- solder
- lead
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はバンブ構造に関し、％にフィルムキャリア方式
（ＴＡＢ方式）で外部リードに半導体重０チップを接続
するのに用いられるバンプに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bump structure, and more particularly to a bump used for connecting a semiconductor heavy-duty chip to an external lead using a film carrier method (TAB method).
フィルムキャリア方式に訃いては、 表面ＫＢ ｎメッ
キが施され７ＨＯＨ製のリードフレームをフイｙｉ−パ
ターン状に固着せしめ、このリードフレームに対して下
側からフェースアップでｘｃチップのムＵバンブ會高速
自動ボンディングすることがある。しかしながらこの場
合には、バンブｉＡＱで構成しているために、Ａｕの使
用量が多く、高価になるという欠点がある。仁のムＵバ
ンブに代えて、表面に薄いムＵメッキを施したＯｕバン
ブを用い、ムＵメッキ膜を有するＯｕリードにボンディ
ングすることもあるが、このボンディングは高温、高荷
重下での熱圧着によるためにその作業が困難である。When using the film carrier method, a 7HOH lead frame with KB n plating on the surface is fixed in a fi-yi-pattern, and an Automatic bonding may occur. However, in this case, since it is made of bamboo iAQ, there is a drawback that a large amount of Au is used, making it expensive. In place of the nickel U bump, an Ou bump whose surface is coated with a thin mu U plating may be used and bonded to an Ou lead with a mu U plating film. The work is difficult because it is crimped.
従って、本発明の目的は、低コス）ＧＣしてボンディン
グ容易なバンブ構造を提供すること１こある。Therefore, one object of the present invention is to provide a bump structure that is low cost and easy to bond.
この目的を連取するために、本発明によれば、バンブ表
面に貴金属層を薄く形成し、更にその上にろう材層を形
成することによって、貴金属の使用量を大幅に滅ら丁と
共に、低温低荷重下で共晶合金を介して迅速にボンディ
ング上行なえるようにしている。In order to achieve this objective, according to the present invention, a thin precious metal layer is formed on the surface of the bump, and a brazing metal layer is further formed on the layer, thereby significantly reducing the amount of precious metal used and reducing the temperature. This enables rapid bonding through the eutectic alloy under low loads.
以下、本発明の実施例【図面について述べる。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
本実施例によれば、第１図に示すように、各棟の半導体
素子を集積化したＩＣチップ１上の絶縁膜（例えば５１
０３躾）２０表面にアルミニウム端子３が設けられ、こ
の端子上にてＯｕ １７−ド４と結合されるバンブ５が
設けられている。バンブ５の下地金属膜６としてけ、Ｏ
ｕ（上層）／Ｃｒ（下層）、Ｐ ｔ ／ ？ １、Ｐ
６ ／ Ｔ １等の積層膜が用いられ、このうち上層膜
ＩＩ′！特にバンブ５一端子３間の導電性を高めるもの
であり、下層膜は端子３及び上層絶縁膜（例えばリン７
ｌ１ケートガラス膜又＃ｌ；ｔｓｉｏｔ！Ｉ）７との接
着性を良くするものである。バンブ５＃ｉ％有の構造か
らなっていて、実質的にバンブの高場を決める厚嘔２０
ｐｍ程度のＭｉ層８と、このＮ１層表面を被０する厚さ
ｔｐ慣程度のＡｕ層９と、この人Ｕ層表面を被覆する厚
さ１μ惧穆度のはんだ（Ｂｎ−Ｐｂ合金）層１゜とによ
って構成ちれている。これらのＮｉ層Ｂ、ムＵ層９及ば
はんだ層ｉｏは共に、電気メッキによって順次形成され
ｔものであり、メッキマスクのパターン及びメッキ条件
に従って容易かつ精度良く形成することができる。一方
、リード４の表面には、Ｑ ｕの酸化を防止するために
薄いａｎ層１１が電気メッキで形成場れてｈる。According to this embodiment, as shown in FIG. 1, an insulating film (for example, 51
03) An aluminum terminal 3 is provided on the surface of the aluminum terminal 20, and a bump 5 is provided on this terminal to be connected to the Ou 17-dead 4. As the underlying metal film 6 of the bump 5, O
u (upper layer)/Cr (lower layer), Pt/? 1.P
A laminated film such as 6/T1 is used, of which the upper film II'! In particular, it enhances the conductivity between the bump 5 and the terminal 3, and the lower layer film is formed between the terminal 3 and the upper insulating film (for example, the phosphor layer 7).
l1 Kate glass membrane #l ; tsiot! I) Improves adhesion with 7. It consists of a structure with 5 #i% of bumps, and the thickness of 20, which essentially determines the high ground of bumps.
An Mi layer 8 with a thickness of approximately pm, an Au layer 9 with a thickness of tp, which covers the surface of this N1 layer, and a solder (Bn-Pb alloy) layer with a thickness of about 1 μm, which covers the surface of this U layer. It is constituted by 1°. The Ni layer B, the U layer 9, and the solder layer IO are all sequentially formed by electroplating, and can be formed easily and accurately according to the pattern of the plating mask and the plating conditions. On the other hand, a thin AN layer 11 is formed on the surface of the lead 4 by electroplating in order to prevent Qu from being oxidized.
上記した如くにバンブ【構成子れば１図示のようにリー
ド４に対しバンブ５をフェースアップに当てがい、ボン
ディング治具で押えながら一定の温度に加熱することＫ
よって、最上のけんだＮ１０が溶融化すると共にその中
１７Ａｕ層９のムＵが溶は込んで共晶化し、はんだの融
点が上昇することになる。ｔたこの共晶はリード番の構
成金属（Ｏｕ）との関にも生じ、リード４とバンブ５と
の接合部にムＵ−はんだ−ＣＵの共晶合金が生成する。As mentioned above, apply the bump 5 face-up to the lead 4 as shown in the figure, and heat it to a constant temperature while holding it with a bonding jig.
Therefore, while the uppermost solder N10 is melted, the 17 Au layer 9 is melted into it and becomes eutectic, raising the melting point of the solder. The eutectic of the octopus is also generated at the connection with the constituent metal (Ou) of the lead number, and a eutectic alloy of MuU-solder-CU is generated at the joint between the lead 4 and the bump 5.
こうして共晶合金を介してバンプ５ｉＰリード４に強固
にボンディングできる上に、ボンディング時にはんだの
融点が上昇するために治具で押えるとはんだの溶融直後
にはんだが丁ぐＫｍまり、治具を外してもバンブ５がも
はやリード４から離脱ゼずに強固に結合重れる仁とにな
る。従って、低廉な材料にて迅速なボンディングが可能
となり、高速テープ（フィルム）キャリア方式を実現で
きる。In this way, it is possible to firmly bond to the bump 5iP lead 4 through the eutectic alloy, and since the melting point of the solder rises during bonding, if you press it with a jig, the solder will get clogged immediately after it melts, so you have to remove the jig. Even if Bamboo 5 no longer separates from Lead 4, it will become a strong bond with Jin. Therefore, rapid bonding is possible using inexpensive materials, and a high-speed tape (film) carrier system can be realized.
これに反して、第１因においてム駿層９を省略してはん
だ層１０ｔ−１１を層８上に直接設けた場合には、ボン
ディング時にはんだが固まるまで治具で押え、その固化
温度まで治具の温度を下降１ぜる必要があるから、ボン
ディング作業の能率が悪くなる。On the other hand, in the first case, if the solder layer 9 is omitted and the solder layer 10t-11 is provided directly on the layer 8, the solder is held down with a jig until it hardens during bonding, and the solder is held down to the solidification temperature. Since it is necessary to lower the temperature of the ingredients, the efficiency of the bonding work is reduced.
本実施例によるバンプ構造は、上記したようにろう材と
してはんだ層ｌＯを設け、下地からのＡｕとの共晶合金
で接合し得るものであるから、ボンディング温度は低く
てよく、かつ低荷重であっても充分な接合強度が得られ
る。従って、高温高荷重の動圧着ボンディングに比べて
、接合強度が安定となり、またボンディング作業も容易
となる。As mentioned above, the bump structure according to this example provides a solder layer lO as a brazing material and can be bonded with a eutectic alloy with Au from the base, so the bonding temperature can be low and the load can be low. Even if there is, sufficient bonding strength can be obtained. Therefore, compared to dynamic pressure bonding which requires high temperature and high load, the bonding strength becomes more stable and the bonding work becomes easier.
しかも、バンブ５のムＵ層９は上記共晶化を生ぜしめる
上に、適度なりッション性もあってボンディング時の応
力を吸収し、ボンディングの信頼性を高める。更に、リ
ード４＠のＳｎ層１１の８ｎもろう材であって上記共晶
合金中に含まれることなるが、バンブ５側にろう材１０
に一形成している関係でＳｎ層１１の厚みを大きくしな
くてもよい。Furthermore, the mu layer 9 of the bump 5 not only causes the above-mentioned eutectic formation, but also has appropriate cushioning properties, absorbs stress during bonding, and improves the reliability of bonding. Furthermore, the 8n of the Sn layer 11 of the lead 4@ is also a brazing material and is included in the eutectic alloy, but the brazing material 10 is on the bump 5 side.
The Sn layer 11 does not need to be thick because the Sn layer 11 is formed in a single layer.
従って、８３層１１がボンディング時に溶融してバンブ
５の周囲で垂れ下がることがない。このたメ、ハンプ５
以外の領域でリード４とチップ１と炉旬絡されることが
なく、信頼性の良いボンディングが可能となる。仮に％
はんだ層１０１にバンプ５側に設けないと丁れば、リー
ド４１ＩＩのＳｎ層１１を厚くしないと充分な接合強度
が得られないが。Therefore, the 83 layer 11 will not melt and sag around the bump 5 during bonding. This tame, hump 5
Since the leads 4 and the chip 1 are not electrically connected in other areas, highly reliable bonding is possible. what if%
If the solder layer 101 is not provided on the bump 5 side, sufficient bonding strength cannot be obtained unless the Sn layer 11 of the lead 41II is made thick.
この場合に＃′ｉｓｎの垂れ下がりＫよって上記の短絡
現象が生じてしまう。In this case, the above-mentioned short circuit phenomenon occurs due to the drooping K of #'isn.
第２図Ｋｉｄ、フィルムキャリア方式で第１図の如くに
ＩＣチップ１ｔリード４にボンディングした状態が示さ
五ている。チップｔＦｉポリイミドキャリアフィルム（
テープ）１２の中央部に形成し几矩形状の開口１３内に
配置δれ、予めエツチングでフィンガーパターンにフィ
ルム１２上に設ｆｆた各リード４の内側端部に対し下側
から当てかわれる。そして、ボンディング治具を用いて
低温低荷重でリード番とチップｌのバンブとが夫々接合
せしめられる。FIG. 2 shows a state in which an IC chip 1t is bonded to leads 4 using the film carrier method as shown in FIG. Chip tFi polyimide carrier film (
The tape is formed in the center of the tape 12 and placed in the rectangular opening 13, and is applied from below to the inner end of each lead 4, which has been etched in a finger pattern on the film 12 in advance. Then, using a bonding jig, the lead numbers and the bumps of the chip 1 are bonded to each other at low temperature and low load.
以上、本発明ｔ−ｆｌ示したが、上述の実施例は本発明
の技術的思（！！に基いて更に変形が可能である。Although the present invention has been described above, the embodiments described above can be further modified based on the technical idea of the present invention.
例えば、リード４のＳｎ層１１は省略してもよい。For example, the Sn layer 11 of the lead 4 may be omitted.
この場合でもバンブ５ａのろう材１０を介して充分な接
合強度が得られるが、リード４のν化防止の面からＳｎ
層１１を形成しておく方が望ましい。Even in this case, sufficient bonding strength can be obtained through the brazing filler metal 10 of the bump 5a, but in order to prevent the lead 4 from becoming ν, Sn
It is preferable to form the layer 11 in advance.
また、バンブ５け上述の３層構造（Ｎｉ−ムｕ −はん
だ）に限らず、種々の材質を用することができる。例え
ば、Ｎｉ層Ｂに代えて、Ｎ１と同様に充分圧硬質で高融
点のＮ １− Ｃｕ合金層、Ｎ１−８ｎ合金層、Ｆｅ層
、Ｏｕ層等を設けることができる。また、Ａ、１層９の
代りに他の貴金属層、例えばムｇＭｉを用いてもよい。Furthermore, the five bumps are not limited to the above-mentioned three-layer structure (Ni-mu-solder), but various materials can be used. For example, in place of the Ni layer B, an N1-Cu alloy layer, a N1-8n alloy layer, an Fe layer, an Ou layer, etc., which are sufficiently compressible and have a high melting point like N1, can be provided. Further, in place of the first layer 9, another noble metal layer, for example, MugMi may be used.
これらの貴金属は、低融点の８ｎと反応してその融点を
上昇せしめ、合金化反応の速度の大きいものであり、し
かもボンディング時の応力を適度に吸収するものであれ
ばよい。、捷九、最上のはんだ層１０は他のろう材、例
えば８ｎｊｎ等で置き換えることができる。These noble metals may react with 8n, which has a low melting point, to raise its melting point, have a high rate of alloying reaction, and can appropriately absorb stress during bonding. The top solder layer 10 can be replaced with another brazing material, such as 8njn.
図面は本発明の実施例を示すものであって、第１図はリ
ー ドにバンブを接触芒ぜた状態の拡大断面図、第２図
はフィルムキャリア方式によりボンディングてれた状慢
の平面図である。
なお、図面に用いられている符号において、１は工０チ
ップ、ａＦｉムを端子、４はＯｕリード、５けバンブ、
７は下地金属、８ｔｊ：Ｎｔ層、ＱｉｊＡｕ層、１０＃
ｉはんだ層、１１はＳｎ層、１２Ｆｉポリイミドフイル
ムでアル。The drawings show an embodiment of the present invention, in which Fig. 1 is an enlarged sectional view of the bump in contact with the lead, and Fig. 2 is a plan view of the state where the bump is bonded by the film carrier method. It is. In addition, in the symbols used in the drawings, 1 is a factory 0 chip, aFim is a terminal, 4 is an O lead, a 5-wire bump,
7 is base metal, 8tj: Nt layer, QijAu layer, 10#
i solder layer, 11 is Sn layer, 12 is Al with Fi polyimide film.
Claims (1)
バンブ構造Ｖｃｉ？いて、実質的にバンプの高−ｇｔ決
める高融点の硬質金属層と、この硬質金属層の表面に形
成された薄い貴金属層と、この貴金属層の表面に形成さ
れた低融点のろう材層とによって構成されていることｔ
−特徴とするバンブ構造。1. Bump structure Vci? provided on the semiconductor substrate and coupled with external leads. A hard metal layer with a high melting point that substantially determines the high gt of the bump, a thin noble metal layer formed on the surface of this hard metal layer, and a brazing material layer with a low melting point formed on the surface of this noble metal layer. It is composed of t
-Featured bump structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56112142A JPS5815252A (en) | 1981-07-20 | 1981-07-20 | Bump structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56112142A JPS5815252A (en) | 1981-07-20 | 1981-07-20 | Bump structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5815252A true JPS5815252A (en) | 1983-01-28 |
Family
ID=14579262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56112142A Pending JPS5815252A (en) | 1981-07-20 | 1981-07-20 | Bump structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815252A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0193128A2 (en) * | 1985-02-25 | 1986-09-03 | Siemens Aktiengesellschaft | Film-mounted circuit and method for its production |
| JPH01238044A (en) * | 1988-03-17 | 1989-09-22 | Nec Corp | Semiconductor device |
| US5027502A (en) * | 1987-12-01 | 1991-07-02 | Mazda Motor Corporation | Automobile assembling method and apparatus therefor |
| KR100432474B1 (en) * | 2000-02-24 | 2004-05-20 | 샤프 가부시키가이샤 | Semiconductor Device |
-
1981
- 1981-07-20 JP JP56112142A patent/JPS5815252A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0193128A2 (en) * | 1985-02-25 | 1986-09-03 | Siemens Aktiengesellschaft | Film-mounted circuit and method for its production |
| EP0193128A3 (en) * | 1985-02-25 | 1987-05-27 | Siemens Aktiengesellschaft | Film-mounted circuit and method for its production |
| US5027502A (en) * | 1987-12-01 | 1991-07-02 | Mazda Motor Corporation | Automobile assembling method and apparatus therefor |
| JPH01238044A (en) * | 1988-03-17 | 1989-09-22 | Nec Corp | Semiconductor device |
| KR100432474B1 (en) * | 2000-02-24 | 2004-05-20 | 샤프 가부시키가이샤 | Semiconductor Device |
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