JPS5814571A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To allow an emitter region to align itself to a base region by a method wherein a first and second non-doped polycrystalline Si layers are employed and P type and N type impurities are implanted in succession, in the process of manufacturing a biplolar type semiconductor device. CONSTITUTION:A thick field oxide film 11 is provided in the periphery of an N<-> type Si substrate 13 and the enclosed surface of the substrate 13 is coated with a thin SiO2 film 14. The entire surface is then covered with the first non-doped polycrystalline Si layer 15. Next, photo resist patterns 16a and 16b are respectively provided on an emitter forming region and a base forming region. P type impurity ion implantation follows for the formation of a P type outer base region 17 in the substrate 13. At the same time, a layer 15' located above the region 17 is made to contain a P type impurity, and layers 15 on the both sides thereof are dismantled together with the resist patterns 16a and 16b. After this, windows 18 and 19 are provided in the film 14, and the second non-doped polycrystalline Si film 20 is grown all over the surface, whereinto N type impurity ions are implanted for the formation of an N<+> type emitter region 24 in contact with the region 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a bipolar semiconductor device, and more particularly to a method of forming an entrant region in the bipolar semiconductor device in self-alignment with a space region.

In bipolar type semiconductor integrated circuits, as a means to improve the degree of integration, the transistors constituting the integrated circuits are formed with an oxide film formed by selective oxidation, such as in an iso-planar structure. A bipolar transistor of isolated structure is used. In bipolar transistors with such an oxide isolation structure, the element isolation region, collector contact window, and base region are formed in alignment using a single photomask, so it is possible to miniaturize the element and improve the degree of integration. However, in this structure, the entrance contact window and the base +1:I contact window, which are also used as the emitter region forming window, are formed by applying a separate layer to the oxide film formed on the base region according to a conventional method. It must be formed using an etching method. Therefore, in the above process, due to errors in mask alignment, the selective oxide film outside the base region may also be etched, and the emitter contact window may be formed deeply and protrude into the selective oxidation portion outside the base region. ,
In such a case, when a two-item region is formed from the emitter contact window by a method such as ion implantation, the electrical power ivy region is formed deep on the side surface of the pace region, so that the space between the collector 0 and the electrical ivy There are times when sheets are generated and the customer yield is reduced.

Therefore, in order to solve the above problems, a conventional method for forming an emitter contact window without using etching means is to form an emitter contact window on a base region 2 defined by a selective oxide film 1, for example, as shown in Figure 1. Polycrystalline silicon layer 3
, and silicon nitride (8
81.1mNa) corresponding to the 4m pattern and the base contact window. After forming the pattern 4b, the polycrystalline silicon layer 3 is selectively thermally oxidized to selectively form a polycrystalline silicon oxide film 5 on the base region 2 as shown in Figure 1(b). 81 above. N, remove patterns 4M and 4b, and #! As shown in Figure 1 <c>, on the base region 2,
Selective oxidation in which the base region 2 is defined by a method such as providing a polycrystalline silicon oxide film 5 having an emitter contact window 6 and a base contact window 7 with a polycrystalline silicon layer 3 disposed at the bottom. J[1 was maintained in a perfect state regardless of the misalignment of the mask, thereby preventing 0-E sheeting during the formation of double ivy stains.

However, in the above conventional method, there is a problem that the reliability of the semiconductor device decreases because the polycrystalline silicon oxide layer has a void and has poor insulation properties compared to a thermally oxidized film of single crystal silicon. There is a problem in that when performing selective thermal oxidation, crystal defects are induced on the surface of the silicon substrate, leading to a decrease in the performance of the semiconductor device.

In order to eliminate the above-mentioned melting point, the present invention improves the insulation properties by forming an insulating film covering the active region with a thermally oxidized film of a single-crystal silicon substrate, and at the same time prevents crystal defects from being induced on the surface of the active region. By forming the base area and the vine area in self-alignment,
A method of manufacturing a semiconductor device having an oxide film isolation structure that prevents a sheet between -n is provided.

That is, the present invention provides a method for manufacturing a bipolar semiconductor device, including a step of forming a thermal oxide film on an active region of a first conductivity type silicon substrate, and forming a first non-doped polycrystalline silicon layer on the thermal oxide film. a step of forming a resist pattern on the wrinkle-free doped polycrystalline silicon layer covering the internal paste formation region and the emitter-shaped radiation region, and selecting a second conductivity type impurity using the resist pattern as a mask; selectively implanting ions to add impurities to the non-doped polycrystalline silicon layer and forming a second conductivity type external space region on the first conductivity type silicon substrate surface; removing the resist /(turn); After that, the non-doped polycrystalline silicon layer located under the resist pattern is selectively etched away, and a second conductivity type polycrystalline silicon layer is formed on the thermal oxide film to cover the upper part of the external space region. forming a silicon pattern, selectively etching the thermal oxide film using the second conductivity type polycrystalline silicon pattern as a mask to form a base contact window and a contact window in the thermal oxide film; a step of selectively introducing second conductivity type impurities from the base contact window and the electric power contact window to form a second conductivity type internal base region in the first conductivity type silicon substrate; The present invention is characterized by comprising a step of selectively introducing impurities of the first conductivity type through the contact window to form an emitter region of the first conductivity type in the internal base region of the second conductivity type.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2(a) to 0).
This will be explained in detail using the process cross-sectional diagram shown in FIG.

When forming a bipolar transistor with a structure in which device isolation is achieved by selective oxidation such as iso-planar using the method of the present invention, selectively Figure 21 (a) to (j)
A semiconductor device is provided by performing a8A processing using .

That is, as shown in FIG. 2(a), the collector region exposed within the base region forming window 12 formed in the selective oxide film 11, for example N + -, is first subjected to normal thermal oxidation on the surface of the silicon substrate 13. An example using the method is 1000 to 4000 (X3
silicon dioxide (8i0.) with the desired thickness of about
A first non-doped polycrystalline silicon layer 15 having a thickness of about 1000 to 2000 (X) is formed on the edge where the film 14 is formed and on the substrate to be processed using a normal chemical vapor deposition (OVD) method. Form.

Next, a photoresist pattern 16 extending over the double vine forming area is formed on the non-φ doped polycrystalline silicon layer 15 using a conventional photo resist pattern 16 as shown in FIG.
Photoresist for recording a and internal pace formation area ψ
After forming the pattern 16b, the non-doped polycrystalline silicon layer 1 is applied to the surface of the N- type silicon substrate 13 using the photoresist patterns 16J1 and 16b as a mask.
5 and 810, selectively implanting P-type impurity ions, for example, boron ions (B+) through the film 14 under desired conditions;
Next, after removing the photoresist patterns 168 and 16b, an activation treatment is performed at, for example, 900 ('C) 11 degrees, and the 13th surface of the N-type silicon substrate is removed as shown in FIG. 2(C). For example, a P-type external base region 17 is formed with a depth of 3000 to 4000 (X) degrees and a surface concentration of approximately (This refers to a base region that is provided to electrically connect the contact region and the functional region of the base without functioning as a base. 1 in the non-dawg polycrystalline silicon layer 15
A P-type polycrystalline silicon layer 15' containing boron 03) at a high concentration of about 1 oll (atom/cII) is formed.If necessary, only the polycrystalline silicon layer can be made to have a high concentration. BP may be ion-implanted. Next, the substrate surface is treated with a potassium hydroxide (KO) aqueous solution of about 10 to 3 Q (wt%), for example, and the non-doped polycrystalline silicon layer 15 is selectively etched away.
! As shown in Figure 2(d), the base contact window 18
.

and a P-type crystalline silicon layer 15' having an emitter contact window 19. Furthermore, since the etching rate ratio of non-doped polycrystalline silicon and P-made polycrystalline silicon to the OH aqueous solution is 1:1 or more, the enlargement of the contact window size in the selective etching process described above is an amount that hardly poses a problem. It is. Next is the top 11! Using the Pal polycrystalline silicon layer 15' as a mask, an etching process of 8 i 0. The film is selectively etched away to remove the S i O as shown in FIG. 2(e).
, base contact window 18 on farm 14 and construction ivy @P
A contact window 19 is formed. Next, a non-doped polycrystalline silicon layer is grown on the substrate surface by a normal OVD method, and as shown in FIG. A second non-doped polycrystalline silicon layer 20 having a thickness of about 100 (X) is formed thereon.

Then, as shown in the 21st @, the second
N″″ through the non-doped polycrystalline silicon layer 20 of
P-board impurity ions, for example, ballast ions (B+) are selectively implanted into the surface of the silicon substrate 13 under desired conditions, and activated at a temperature of, for example, about 900 (C) for a desired period of time.
It has a depth of about 00 (X) and a depth of 10" (atm/c
P-type internal base region #, 2 having a surface concentration of about Wt]
1 and 22 are formed.

Next, as shown in FIG. 2(h), the base contact window 18 is covered with a photoresist pattern 23, and a P-type film is formed through the second non-doped polycrystalline silicon layer 20 through the emitter contact window 19. Internal pace area 2
N-type impurity ions, such as deep violet ions (As''), are selectively implanted into the second surface under desired conditions, and then the photo
After removing the resist pattern 23, the resist pattern 23 is activated at a temperature of about 900 CC] for a desired time, and as shown in FIG.
An N+ type emitter region 24 having a depth of approximately X) is formed.

Note that the N+ type emitter region 24 is self-aligned with the P-type internal space region 22 via the emitter contact window 19 as described above, and is formed shallower than the P-type internal base region 22, so that the N+ type emitter region 24 is The Pg internal space region 22 is always interposed between the ivy region 24 and the N-type silicon substrate 13, which is the collector region, and no c-g sheet is generated. Next, as shown in FIG. 20), for example, aluminum wiring 25 is formed on the pace fist contact window 18 and the double ivy contact window 19 by a conventional method, and
After selectively etching and removing the polycrystalline silicon layers 201 and 15' exposed between the wires using the aluminum wiring 25 as a mask, the cover insulation was incorrectly formed, although it is not known, and a bipolar film made of oxidized materials was formed. type semiconductor device is completed.

At this point, I would like to add an explanation about the collector contact area.
sNJ! The collector contact region is usually formed by implanting N-type impurity ions with the base forming window covered with a resist group, prior to forming the 1j respace region. In addition, the implantation of P-type impurity ions for forming the base region is carried out with resist applied over the contact window of the collector through which the base region is formed. Also, as in the usual method, the N-type impurity implanted when forming the vine region is simultaneously implanted into the collector contact window. Furthermore, the second non-doped polycrystalline silicon layer mentioned above is also formed within the collector contact window.In addition, in the above *example, the N+ type power supply vine region was formed by ion implantation. , the entrant region can also be formed by solid phase-solid phase diffusion from phosphosilicate glass (P2O)M.

Further, the method of the present invention can also be applied to a PNP type semiconductor device. Further, although the above description has been made by taking the oxidation-isolation structure as an example, it is obvious that the present invention can be applied to other element isolation structures such as junction isolation, VIP, and 08 parts.

As explained above, according to the present invention, the insulating film on the ivy region and the base region in a bipolar semiconductor device can be formed of a silicon dioxide film formed by thermal oxidation of single crystal silicon, and moreover, the base region and the emitter region can be formed by self-alignment, the insulation performance of the insulation film is improved, and (collector emitter) shielding is also prevented.Therefore, the reliability and manufacturing yield of bipolar semiconductor devices are improved. Improves performance.

[Brief explanation of the drawing]

FIGS. 1(1) to (C) are process sectional views of a conventional method, and FIGS. 2(a) to 0) are process sectional views of an embodiment of the method of the present invention. In the figure, 11 is a selective oxide film, 12 is a base region window,
13 is a N'''' silicon substrate, 14 is a silicon dioxide film, 15 is a first non-doped polycrystalline silicon layer, 15'
is a P-type polycrystalline silicon layer, 16a. 16b, 23 are photo-resist patterns, 17 are P
Mold external base area, 18, pace fist contact window, 19
20 is a second non-doped polycrystalline silicon layer; 21 and 22 are P-type internal base regions;
24 is the N+ type emitter value range, 25 is the aluminum wiring,
B+ indicates boron ion, As+ indicates arsenic ion・
□ Akira 1 Senko 2 Diagram

Claims (1)

[Claims] A method for manufacturing a bipolar semiconductor device includes: forming a thermal oxide film on an active region of a first conductivity type silicon substrate; forming a first non-doped polycrystalline silicon layer on the thermal oxide film; a step of forming a resist pattern on the non-doped polycrystalline silicon layer covering the internal space formation region and the emitter formation region, respectively;
- selectively ion-implanting a second conductive type impurity using the pattern as one mask, adding the impurity to the non-doped polycrystalline silicon layer, and adding a second conductive type external base to the first conductive type silicon body surface; After removing the resist pattern, the non-doped polycrystalline silicon layer located under the resist pattern is selectively etched away and etched onto the thermal oxide film. A second conductivity type polycrystalline silicon layer extending over the external space region.
forming a pattern; selectively etching the thermal oxide film using the second conductive polycrystalline silicon pattern as a mask to form a pace contact window and a construction ivy contact window in the thermal oxide film; , forming a second conductive inner space region in the first conductive silicon substrate by selectively introducing impurities of a second conductivity type through the base fist contact window and the double ivy contact window; 1. A method of manufacturing a semiconductor device, comprising the step of selectively introducing a first conductive source impurity through a contact window to form a first conductive type emitter region within the second conductive type internal space region.