JPS5943099B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a bipolar semiconductor device, and more particularly to a method of forming an emitter region of the bipolar semiconductor device in self-alignment with a base region.

In bipolar semiconductor integrated circuits, as a means to improve the degree of integration, the transistors that make up the integrated circuit have a structure in which elements are isolated by an oxide film formed by selective oxidation, such as an iso-planar structure. Bipolar transistors are used.

In bipolar transistors with such an oxide isolation structure, the element isolation region, the collector contact window, and the base region are aligned and formed using a single photomask, which makes it easy to miniaturize the element and improve the degree of integration. Although this structure is extremely advantageous, the emitter contact window and the base contact window, which are also used as emitter region forming windows, are formed by separately photo-etching the oxide film formed on the base region according to the usual method. It must be formed using Therefore, in the above process, due to errors in mask alignment, the selective oxide film outside the base region may also be etched, and the emitter contact window may protrude into the selective oxide film portion outside the base region and be formed deeply. In such a case, when an emitter region is formed by a method such as ion implantation from the emitter contact window,
Since the emitter region is formed deeply on the side surface of the base region, a short circuit occurs between the collector C and the emitter E, resulting in a decrease in manufacturing yield. Therefore, in order to solve the above problems, a conventional method for forming an emitter contact window without using etching means is shown in Fig. 1a.
As shown in FIG. 2, for example, a polycrystalline silicon layer 3 is formed on a base region 2 defined by a selective oxide film 1, and a nitrided silicon layer 3 corresponding to an emitter contact window (emitter formation window) is formed on the polycrystalline silicon layer 3. After forming a silicon (Si3N4) pattern 4a and a Si3N4 pattern 4b corresponding to the base contact window, the polycrystalline silicon layer 3 is selectively thermally oxidized to form a polycrystalline silicon oxide film on the base region 2, as shown in FIG. 1b. 5 and then the Si3N
4 patterns 4a and 4b are removed, and a polygonal pattern is formed on the base region 2, as shown in FIG. A selective oxide film 1 defining a base region 2 by a method such as providing a crystalline silicon oxide film 5.
This prevents CE shot during formation of the emitter region by keeping it in a perfect state regardless of mask misalignment.

However, in the above conventional method, there is a problem that the reliability of the semiconductor device decreases because the polycrystalline silicon oxide film is porous and has inferior insulating properties compared to the thermal oxide film of single crystal silicon, and the selection of the polycrystalline silicon layer is difficult. There has been a problem in that when performing thermal oxidation, crystal defects are induced on the surface of the silicon substrate, leading to a decline in the performance of the semiconductor device.

In order to eliminate the above-mentioned problems, the present invention improves the insulation properties by forming an insulating film covering the active region with a thermally oxidized film of a single-crystal silicon substrate, and at the same time prevents crystal defects from being induced on the surface of the active region. By forming the base region and emitter region in self-alignment, C.
A method for manufacturing a semiconductor device having an oxide film isolation structure that prevents shorts between -E is provided.

According to the present invention, a step of forming an insulating layer on a semiconductor substrate having a first conductivity type, a step of forming a polycrystalline semiconductor layer on the insulating layer, and a step of forming a mask layer formed on the polycrystalline semiconductor layer. A step of introducing a second conductivity type impurity into the semiconductor substrate as a mask, a step of removing the mask layer and the polycrystalline semiconductor layer under the mask layer, and a step of removing the insulating layer using the remaining polycrystalline semiconductor layer as a mask. a step of forming an opening in the semiconductor substrate, a step of introducing a second conductivity type impurity into the semiconductor substrate through the opening, and a step of selectively introducing a first conductivity type impurity into the region where the second conductivity type impurity is introduced through the opening. A method of manufacturing a semiconductor device is provided, which includes a step of introducing.

Hereinafter, one embodiment of the present invention will be explained in detail using process cross-sectional views shown in FIGS. 2a to 2j.

When forming a bipolar transistor having a structure in which element isolation is achieved by selective oxidation such as iso-planar using the method of the present invention, first, although not shown, a normal selective oxidation method is used to form a lower layer, for example, an N+ type buried layer. An oxide film region window is formed on the surface of an N-type silicon substrate having a substrate having a conductive structure, etc., for separating the elements and the collector/contact region/base region. Thereafter, the N-type silicon substrate surface exposed in the base region window of the oxide film is selectively subjected to the process described with reference to FIGS. 2a to 2j to provide a semiconductor device. That is, as shown in FIG. 2a, the collector region exposed within the base region forming window 12 formed in the selective oxide film 11, for example, the surface of the N-type silicon substrate 13, is first etched using a normal thermal oxidation method. For example, after forming a silicon dioxide (SiO2) film 14 having a desired thickness of about 1,000 to 4,000 [λ], it is deposited on the substrate to be processed using normal chemical vapor deposition (CVD).
) method to form a first non-doped polycrystalline silicon layer 15 having a thickness of about 1000 to 2000 [λ].

Next, using a normal photo process, a photo resist pattern 16a is formed on the non-doped polycrystalline silicon layer 15 to cover the emitter formation region as shown in FIG. 2b.
After forming a photoresist pattern 16b covering the internal base formation region, the non-doped polycrystalline silicon layer 15 and P-type impurity ions, such as boron ions (B+), are selectively implanted under desired conditions through the SiO2 film 14, and then, after removing the photoresist patterns 16a and 16b, activation treatment is performed at, for example, about 900°C. go and
As shown in FIG.
A P-type external base region 17 having a surface concentration of about 19 [AtOm/~] is formed. (The external base region refers to a base region that does not directly function as a base but is provided to electrically connect the contact region and functional region of the base.)
The regions of the non-doped polycrystalline silicon layer 15 that are not covered by the patterns 16a and 16b have 1020 to 102
A P-type polycrystalline silicon layer 15' containing boron (B) at a high concentration of about 1 [AtOm/d] is formed. If necessary, BF2 can be added to make only the polycrystalline silicon layer highly concentrated.
may be ion implanted. Next, the surface of the substrate is coated with potassium hydroxide (KOH) of about 10 to 30 [Wt%].
Treated with an aqueous solution, non- The doped polycrystalline silicon layer 15 is selectively etched away to form a base contact window 18 and an emitter contact window 1 as shown in FIG.
9 is formed as a P-type polycrystalline silicon layer 15'. The etching rate ratio of non-doped polycrystalline silicon and P-type polycrystalline silicon to the KOH aqueous solution is 10:
1 or more, the enlargement of the contact window size in the selective etching step is such an amount that it hardly causes any problem. Next, using the P-type polycrystalline silicon layer 15' as a mask, the SiO2 film is etched by an etching method having a direction perpendicular to the substrate surface, such as reactive ion etching using methane trifluoride (C3). is selectively etched away to remove the S as shown in FIG.
A base contact window 18 and an emitter contact window 19 are formed in the iO2 film 14. Next, a non-doped polycrystalline silicon layer is grown on the substrate surface by a conventional CVD method, and as shown in FIG. A second non-doped polycrystalline silicon layer 20 having a thickness of about [λ] is formed. Next, as shown in FIG. 2g, a film is selectively applied to the surface of the N-type silicon substrate 13 through the second non-doped polycrystalline silicon layer 20 through the base contact window 18 and the emitter contact window 19 under desired conditions. Generally, P-type impurity ions such as boron ions (B
+) and activated for a desired time at a temperature of about 900 [°C] to form a P-type interior having a depth of about 3000 [λ] and a surface concentration of about 1019 [Atm/d]. Base regions 21 and 22 are formed. Next, as shown in FIG. 2h, the base contact window 18 is photo-photographed.
Covering with a resist pattern 23, N-type impurity ions, for example, arsenic ions, are selectively applied to the surface of the P-type internal base region 22 under desired conditions through the emitter contact window 19 and the second non-doped polycrystalline silicon layer 20. (As+
), then the photoresist pattern 2
After removing the P-type internal base region 2, the P-type internal base region 2 is activated at a temperature of about 900[° C.] for a desired period of time as shown in FIG.
An N+ type emitter region 24 having a depth of, for example, about 1000 [λ] is formed on the two surfaces. Note that the N+ type emitter region 24 is self-aligned with the P-type internal base region 22 via the emitter contact window 19 as described above, and is formed shallower than the P-type internal base region 22, so that the N-type emitter region 24 and the N-type silicon substrate 1 which is the collector region.
There is always a P-type internal base region 22 between C and C.
-E-shot does not occur. Next, as shown in FIG. 2J, for example, an aluminum wiring 25 is formed on the base contact window 18 and the emitter contact window 19 by a conventional method, and using the aluminum wiring 25 as a mask, the polycrystals exposed between the wirings are formed. After selectively etching away the silicon layers 20 and 15', a cover insulating film is formed (not shown), and a bipolar semiconductor device with an oxide film isolation structure is completed. Here, the collector
To add an explanation about the contact area, when thermally oxidizing the silicon substrate surface exposed within the base region window, the Si3N4 film is left in the collector/collector window, and the collector/contact region is As usual, prior to forming the base region, the base region is formed by implanting N-type impurity ions while covering the base formation window with a resist film.

In addition, the implantation of P-type impurity ions for forming the base region is performed with the collector contact window covered with resist as usual. Also, as in the usual method, the N-type impurity implanted when forming the emitter region is simultaneously implanted into the collector contact window. The second non-doped polycrystalline silicon layer described above is also formed within the collector contact window. Furthermore, in the above embodiment, the N+ type emitter region was formed by ion implantation, but the emitter region can also be formed by solid phase solid phase diffusion from a phosphosilicate glass (PSG) film.

Further, the method of the present invention can also be applied to a PNP type semiconductor device.

Further, although the above description has been made using an oxide film isolation structure as an example, it is obvious that the present invention can also be applied to other element isolation structures such as junction isolation, IP, and OST. As explained above, according to the present invention, the insulating film on the emitter region and the base region in a bipolar semiconductor device can be formed of a silicon dioxide film formed by thermal oxidation of single crystal silicon, and the base region and the emitter region can be Since it can be formed by self-alignment, the insulating performance of the insulating film is improved and (collector emitter) shorting is also prevented.

Therefore, the reliability and manufacturing yield of bipolar semiconductor devices are improved.

[Brief explanation of drawings]

1A to 1C are process sectional views of a conventional method, and FIGS. 2A to 2J are process sectional views of an embodiment of the method of the present invention. In the figure, 11 is a selective oxide film, 12 is a base region window,
13 is an N-type silicon substrate, 14 is a silicon dioxide film,
15 is a first non-doped polycrystalline silicon layer; 15' is a P-type polycrystalline silicon layer; 16a, 16b, and 23 are photoresist patterns; 17 is a P-type external base region;
8 is a base contact window, 19 is an emitter contact window, 20 is a second non-doped polycrystalline silicon layer, 2
1 and 22 are P-type internal base regions, 24 is N+ type emitter region, 25 is aluminum wiring, B+ is boron ion,
As+ represents an arsenic ion.

Claims (1)

[Claims] 1 a step of forming an insulating layer on a semiconductor substrate having a first conductivity type, a step of forming a polycrystalline semiconductor layer on the insulating layer,
introducing a second conductivity type impurity into the semiconductor substrate using the mask layer formed on the polycrystalline semiconductor layer as a mask;
removing the mask layer and the polycrystalline semiconductor layer under the mask layer; forming an opening in the insulating layer using the remaining polycrystalline semiconductor layer as a mask; A method for manufacturing a semiconductor device, comprising the steps of introducing a conductivity type impurity, and selectively introducing a first conductivity type impurity into the second conductivity type impurity introduction region through the opening.