JPS58138045A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58138045A
JPS58138045A JP57020812A JP2081282A JPS58138045A JP S58138045 A JPS58138045 A JP S58138045A JP 57020812 A JP57020812 A JP 57020812A JP 2081282 A JP2081282 A JP 2081282A JP S58138045 A JPS58138045 A JP S58138045A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
adhesive
pattern
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57020812A
Other languages
Japanese (ja)
Inventor
Bunji Takeuchi
竹内　文二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57020812A priority Critical patent/JPS58138045A/en
Publication of JPS58138045A publication Critical patent/JPS58138045A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve the efficiency of a wire bonding work and the reliability of a wire bonding by a method wherein, using a conductive adhesive of color different from the wiring pattern of a semiconductor chip, the semiconductor chip is adhered in a process of die bonding of the semiconductor such as an IC and an LSI. CONSTITUTION:Bonding parts 16 and 16' electrically connected to lead frames 17 and 17' and patterned are provided in the recess 13 of a package 12 formed in an integral body with the lead frames 17 and 17'. The black epoxy adhesive 18 is applied on the bottom surface of the recess 13. Thus, when conductive black epoxy is used as the adhesive 18 for die bonding, and the semiconductor chip 11 is looked from the upper surface, the base of the back surface of the pattern by Al alloy is appeared black, and accordingly the pattern can be easily recognized.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体テップのマウント部を改善した例えば
ＩＣ，ＬＳＩなどの半導体装置Ｍ６壽４１１１か社に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device such as an IC or an LSI, which has an improved mounting portion of a semiconductor chip.

〔発明の技術的背景〕[Technical background of the invention]

従来、半導体装置例えば（Ｃ，Ｌ８Ｉなどは。 Conventionally, semiconductor devices such as (C, L8I, etc.) have been used.

第１図に示すように構成される。１１は、ＩＣ。It is constructed as shown in FIG. 11 is IC.

ＬＳＩなどの所定の機能を持ち／４ターニングされた半
導体チップであり、半導体装置の）譬ツケージＪ２の凹
部ＪＪにマウントされている。そしてこの半導体チップ
ＪＪ上にノ青ターニングされた電極部（以下がンデイン
グノヤツド）１４畠。It is a /4 turned semiconductor chip having a predetermined function such as an LSI, and is mounted in a recess JJ of a parallel cage J2 of a semiconductor device. Then, on this semiconductor chip JJ, there are 14 electrode portions (hereinafter referred to as turning electrodes).

Ｊ　４　ｂ−・・はがンデイングワイヤ１６畠、Ｉｌｂ
。J 4 b--Haganding wire 16 Hatake, Ilb
.

・・・によって、リードフレームＪＦａ、ＪＦｂ＝に電
気的に接続される一ン９ディンｒ部１６ｍ。. . , the one-in-nine-din r portion 16m is electrically connected to the lead frames JFa and JFb=.

１１ｒｂ・・・が設けられている。また、この半導体テ
ップ１１をマウントされたパッケージＩＪの凹部ＩＪは
１図示されないキャップなどによって例えば気書封止法
、樹脂゛封止法などで封止される。11rb... are provided. Further, the recess IJ of the package IJ on which the semiconductor chip 11 is mounted is sealed with a cap (not shown) by, for example, a gas sealing method, a resin sealing method, or the like.

〔背景技術の間融点〕[Melting point of background technology]

このように構成された半導体装置が例えば８０８型のも
のであり、半導体チツ７’ＪＪがサファイヤなどの透明
体絶縁基板上に半導体膜を形成した構造のものとすると
、半導体膜が充分に薄いために、半導体チップ１１の上
面からチップ裏向が透けて晃える。また、この半導体テ
ツブ１１は１表面にアルミ合金による配線／昔ターンが
施され、裏面が導電性銀ペーストによってノ譬ツゲージ
１２に接着されている。そして。If the semiconductor device configured in this way is, for example, an 808 type, and the semiconductor chip 7'JJ has a structure in which a semiconductor film is formed on a transparent insulating substrate such as sapphire, the semiconductor film is sufficiently thin. In addition, the back side of the semiconductor chip 11 can be seen through the top surface of the semiconductor chip 11. Further, this semiconductor tube 11 has aluminum alloy wiring/contours applied to one surface, and is bonded to the test gauge 12 on the back surface with conductive silver paste. and.

この導電性銀ペーストによる銀色と、アルミ合金による
パターンの色が同系統の色であり、上面から半導体テッ
プ１１を見た場合、裏面の導電性銀ペーストの色のため
に配線／＃ターンが識別しに（い。したがって、−ンデ
インダ／ｆツド１４蟲、１４ｂ、・・・をｌンデインダ
ヮイヤ１５ｍ。The silver color created by this conductive silver paste and the color of the pattern created by the aluminum alloy are the same color, and when looking at the semiconductor chip 11 from the top surface, the wiring/# turn can be identified due to the color of the conductive silver paste on the back surface. (I. Therefore, -ndeinda/f tsudo 14 insects, 14b,...) lndeindia 15m.

１５ｂ、・・・で接続するワイヤＩンデインダ工程１行
５１１．配線）中ターン上の一ンデインダ／譬ツド１４
ｍ、１４ｂがわかりに＜＜１作業能率と。15b, . . . wire I inductor process 1 row 511. Wiring) One index/parameter 14 on the middle turn
m, 14b is clearly <<1 work efficiency.

−ンデイング部の精度に悪影響を与えていた。- This had a negative effect on the accuracy of the modeling part.

〔発明の目的〕[Purpose of the invention]

この発明は、上記のような点に鑑みなされたもので、透
明体絶縁基板を用いた半導体デツプの表面ノ譬ターンが
より鮮明に見えるようにして。The present invention was made in view of the above-mentioned points, and it is possible to more clearly see the pattern on the surface of a semiconductor depth using a transparent insulating substrate.

ｌンディング作業をしやすくした半導体装置を提供しよ
うとするものである。The present invention is intended to provide a semiconductor device that is easy to perform a loading operation.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係る半導体装置は、透明体絶縁基板
上に半導体膜が形成されている半導体チップにおいて、
この半導体チップ上の配線ノｆターンとは異なる色彩の
接着剤を用いて〆イがンデイング（マウンＦ）がなされ
るようなものである。That is, the semiconductor device according to the present invention includes a semiconductor chip in which a semiconductor film is formed on a transparent insulating substrate.
It is like mounting (mounting) the wiring on the semiconductor chip using an adhesive of a different color from that of the wiring F-turn.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して、この発明の一実施例をその組立て
工程に基き説明する。第２図の（１）〜（ｄ）は、その
組み立て工程を説明するもので、第２図（１）において
１２はリードフレーム１１゜１１′と一体的に形成され
た例えばセラミックによるノ譬ツケージである。／量ツ
ケージ１１の凹部１３にはリードフレームＪ　Ｆ　、　
Ｊ　Ｆ’と電気的に接続してパターニングされた一ンデ
イング部Ｊ　６　、　Ｊ　６’が設けられている。また
、この凹部１１の底面には図に示すように黒色工４キシ
による接着剤１１を塗る。An embodiment of the present invention will be described below based on its assembly process with reference to the drawings. 2 (1) to (d) explain the assembly process. In FIG. 2 (1), 12 is a miniature cage made of, for example, ceramic, which is integrally formed with the lead frame 11° 11'. It is. /In the recess 13 of the cage 11, a lead frame JF,
Patterned binding portions J6 and J6' are provided to be electrically connected to JF'. Further, the bottom surface of the recess 11 is coated with an adhesive 11 made of black lacquer 4, as shown in the figure.

次に第２図（ｂ）に示すように上記接着剤ＩＩの塗られ
た向上に半導体テツｆｘｓｖ装置し、〆イがンデインダ
を行なう。この半導体チップ１１は、前記したようにサ
ファイヤなどの透明体絶縁基板１＃上に、半導体膜１−
が形成されており、ここに例えばアルミ合金によるパタ
ーンが施されている。アルミ合金によるパターンは半導
体膜ｊＯの上面にのみ施されている場合もあれば、多層
構造となっている場合もあり。Next, as shown in FIG. 2(b), the surface coated with the adhesive II is applied to a semiconductor TFT fxsv device, and a final step is performed to perform indinder. As described above, this semiconductor chip 11 is made of a semiconductor film 1-1 on a transparent insulating substrate 1# made of sapphire or the like.
is formed, and a pattern made of, for example, an aluminum alloy is applied thereto. The aluminum alloy pattern may be applied only to the upper surface of the semiconductor film jO, or may have a multilayer structure.

この／昔ターンの一部は金属面の露出した一ンデインダ
Ｉｆツドとなっている。A part of this turn is an exposed metal surface.

このようにして坐導体テツ７’ＪＪがマクントされると
、第２図（ｃ）に示すように半導体デッ１１１の一ンデ
ィンダ／４ツドＪ　４　、　Ｊ　４’と、／４ツケツジ
１１の凹部１１の周囲に並んだリードフレームの一ンデ
ィンダ部Ｊ　＃　、　Ｊ　＃’とを極細アルミ線あるい
は極細金線による一ンディンダヮイヤＪ　ｊ　、　Ｊ　
Ｊ’で接続するがンディンダが行なわれる。この−ンデ
ィングが終了すると、第２図（−）のようにノ臂ツヶー
ジ１１にキャラｆｌ／１がかぶせられ、封止される。そ
して１図には示されていないが、！−ｒフレームｓｒ、
ｓｒＩの不要な枠体を切り、リードフレームＪ　Ｆ　、
　Ｊ　Ｆ’を曲げるなどして組立てを完了する。When the seat conductor strips 7'JJ are mounded in this manner, the semiconductor deck 111 has one-way diagonal/fourth dots J4, J4' and the recessed portion 11 of the four-way foot 11, as shown in FIG. 2(c). The one-dinder parts J#, J#' of the lead frame lined up around the lead frame are connected with one-dinder parts Jj, J made of ultra-fine aluminum wire or ultra-fine gold wire.
Connection is made with J', but undinda is performed. When this ending is completed, the character fl/1 is placed over the armpit cage 11 and sealed as shown in FIG. 2 (-). And although it is not shown in Figure 1,! −r frame sr,
Cut the unnecessary frame of srI, and make the lead frame JF,
Complete the assembly by bending JF'.

このようにこの実施例では導伝性黒色ニーキシを〆イ一
ンディンダの接着剤１１として用いており、上面より半
導体ｔツｆ１Ｊを見るとアルミ合金による／譬ターンの
裏面にある地が黒（見え、）譬ターンが容易に識別でき
るようになる。As described above, in this embodiment, conductive black resin is used as the adhesive 11 of the finishing plate, and when looking at the semiconductor T-T-F1J from the top surface, the base on the back side of the aluminum alloy plate is black (not visible). ,) The parable turns can be easily identified.

したがって、ワイヤがンデインダ作業の能率が向上し、
その際の位置決めなどを正確に行なうことができるよう
になる。Therefore, the efficiency of wire-induring work is improved,
At that time, positioning etc. can be performed accurately.

なお、〆イがンディンダに用いる接着剤は。In addition, what kind of adhesive is used for the closing part?

アルミ合金など半導体膜表面のパターン用金属の色と興
なる色の接着剤を用いればよ（、たとえば黒色エポキシ
系接着剤などは表面の／臂ターンが、より鮮明になるの
で最も良いが、一般に明度彩度の低い色であれば他のも
のでも容易なワイヤーンディンダ作業が可能である。。It is best to use an adhesive with a color that matches the color of the pattern metal on the surface of the semiconductor film, such as aluminum alloy (for example, black epoxy adhesive is best because it makes the surface/arm turn more clear, but in general Wire-and-dinder work is possible with other colors as long as they have low brightness and saturation.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明では、ＩＣ，Ｌ８Ｉなとの半導体
装置のグイーンディンダ工程で、半導体チップの配線／
臂ターンと興なる色彩の導電性接着剤を用いて半導体チ
ップを接着することにより、ワイヤがンデインダ作業の
能率およびワイヤーンデインダの信頼性の向上した半導
体装置を提供することができる。As described above, in this invention, wiring/
By bonding semiconductor chips using a conductive adhesive of a color that differs from the arm turn, it is possible to provide a semiconductor device in which the efficiency of the wire winding work and the reliability of the wire winding work are improved.

なお、上記実施例では、ＤＩＰ［半導体装置について説
明したが、透明体基板上に形成され）譬ターニングされ
た半導体チップを用いるものであれば、他の型のものや
、ＩＣ，Ｌ８Ｉ以外のものにも適用できる。In addition, in the above embodiment, as long as a DIP (a semiconductor device was explained, but it is formed on a transparent substrate) and a turned semiconductor chip is used, other types or devices other than IC and L8I may be used. It can also be applied to

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は半導体装置の構造を説明する斜視図。 第２図（ａ）〜（ｄ）はこの発明の一実施例に係る半導
体装置の組み立て工程を説明する断面図である。 １１・・・半導体チップ、１１−／譬ツケージ。 １１．１１’、Ｉｉｍ、１１ｂ＝ｄｌンデイン／　１フ
イヤ、Ｊ−，３１’、Ｊ＃１１．Ｊξ−・−一ンデイン
ダノダツド、１ｍ−接着剤。FIG. 1 is a perspective view illustrating the structure of a semiconductor device. FIGS. 2(a) to 2(d) are cross-sectional views illustrating the assembly process of a semiconductor device according to an embodiment of the present invention. 11...Semiconductor chip, 11-/analogue. 11.11', Iim, 11b=dlundein/1fire, J-, 31', J#11. Jξ-・-1 indiandanodatsud, 1m-adhesive.

Claims (1)

【特許請求の範囲】[Claims] 透明体絶縁基板上に配線パターンが施された半導体膜な
有する半導体チップと、この半導体チップのがンデイン
ダパッドに〆ンデインダワイヤで接続されたリードを含
み上記半導体テップを取り付けられる／ｌツケージとを
備え、この・豐ツケージに対して上記半導体テップをそ
の配線／ｆターンとは興なる色彩の接着剤によって接着
するようにしたことを特徴とする半導体装置。The present invention comprises a semiconductor chip having a semiconductor film having a wiring pattern on a transparent insulating substrate, and a cage to which the semiconductor chip is attached, and the semiconductor chip includes leads connected to conductor pads with conductor wires. - A semiconductor device characterized in that the above-mentioned semiconductor chip is adhered to the support cage using an adhesive of a different color from that of the wiring/f-turn.
JP57020812A 1982-02-12 1982-02-12 Semiconductor device Pending JPS58138045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57020812A JPS58138045A (en) 1982-02-12 1982-02-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57020812A JPS58138045A (en) 1982-02-12 1982-02-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58138045A true JPS58138045A (en) 1983-08-16

Family

ID=12037444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57020812A Pending JPS58138045A (en) 1982-02-12 1982-02-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58138045A (en)

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