JPS6032770Y2 - semiconductor element - Google Patents
semiconductor elementInfo
- Publication number
- JPS6032770Y2 JPS6032770Y2 JP1980057332U JP5733280U JPS6032770Y2 JP S6032770 Y2 JPS6032770 Y2 JP S6032770Y2 JP 1980057332 U JP1980057332 U JP 1980057332U JP 5733280 U JP5733280 U JP 5733280U JP S6032770 Y2 JPS6032770 Y2 JP S6032770Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- conductor layer
- printed circuit
- circuit board
- stem
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
Landscapes
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
本考案は、半導体チップの電極とステムのリード端子と
をワイヤボンディングして成る半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor element formed by wire bonding electrodes of a semiconductor chip and lead terminals of a stem.
この種の半導体素子における半導体チップとステムのリ
ード端子とのワイヤボンディングには、リード端子先端
を金又は銀メッキしておくことが必要である。For wire bonding between the semiconductor chip and the lead terminals of the stem in this type of semiconductor device, it is necessary to plate the tips of the lead terminals with gold or silver.
この場合、リード端子の先端のみを部分的にメッキする
ことは、特別な治具を要し、且つ、手間がかかるため、
従来は、リード端子を有するステム全体を金又は銀メッ
キしている。In this case, partially plating only the tip of the lead terminal requires a special jig and is time-consuming.
Conventionally, the entire stem including the lead terminals is plated with gold or silver.
ところが、金、銀等の貴金属は、高価であり、特に、近
年は高騰しているため、半導体素子の価格を上昇させる
大きな要因となっている。However, precious metals such as gold and silver are expensive, and their prices have been rising in recent years, which is a major factor in increasing the prices of semiconductor devices.
本考案は、斬かる問題点を解決すべくなされたもので、
リード端子接続用の導体層を有し且つ該導体層の全部又
は一部にボンディング可能領域を形成して成るプリント
基板を介して半導体チップとリード端子とを接続するよ
う構成して、簡単な構造により金等の貴金属の使用量を
減少し、安価に製造し得る半導体素子を提供することを
目的とする。This invention was created to solve a serious problem.
A simple structure is provided in which the semiconductor chip and the lead terminals are connected through a printed circuit board that has a conductor layer for connecting the lead terminals and has a bondable area formed in all or part of the conductor layer. It is an object of the present invention to reduce the amount of precious metals such as gold used and to provide a semiconductor element that can be manufactured at low cost.
即ち、本考案は、リード端子を有するステム上に半導体
チップを載置固定し、該半導体チップの電極の少なくと
も一つをリード端子とワイヤボンディングして戒る半導
体素子において、リード端子接続用の導体層を有し且つ
該導体層の全部又は一部にボンディング可能領域を形成
して成るプリント基板を、所定リード端子毎に上記ステ
ム上に載置固着して上記リード端子と導体層とを接続し
、且つ、上記半導体チップの電極とボンディング可能領
域とをワイヤボンディングして成るものである。That is, the present invention provides a semiconductor device in which a semiconductor chip is placed and fixed on a stem having lead terminals, and at least one of the electrodes of the semiconductor chip is wire-bonded to the lead terminals. A printed circuit board having a layer and a bondable area formed in all or part of the conductor layer is placed and fixed on the stem for each predetermined lead terminal to connect the lead terminal and the conductor layer. , and the electrode of the semiconductor chip and the bondable region are wire-bonded.
以下、本考案を図面に示す実施例に基づいて説明する。Hereinafter, the present invention will be explained based on embodiments shown in the drawings.
第１図は本考案の一実施例を示す平面図、第２図は上記
第１図のＡ−Ａ断面図である。FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA in FIG. 1.
これらの図において本考案半導体素子は、リード端子２
を有するステム１と、該ステム１上に載置されるプリン
ト基板３と、該プリント基板３上に載置される半導体チ
ップ７とから構成される。In these figures, the semiconductor device of the present invention has lead terminals 2
It is composed of a stem 1 having a structure, a printed circuit board 3 placed on the stem 1, and a semiconductor chip 7 placed on the printed circuit board 3.
上記ステム１は、金属製の基台１ａに絶縁層１ｂを介し
てリード端子２を取付けて戊り、半導体チップ７を取付
は後、図示しない金属キャップ等を固着して半導体チッ
プを封止し、半導体素子を構成する。The stem 1 is constructed by attaching lead terminals 2 to a metal base 1a via an insulating layer 1b, attaching a semiconductor chip 7, and then sealing the semiconductor chip by fixing a metal cap (not shown) or the like. , constitutes a semiconductor element.
上記プリント基板３は、例えばガラスエポキシ樹脂等の
絶縁板上に、周知の手段により、銅等から成る導体層４
を設けたもので、半導体チップ７とリード端子２との接
続を行なうためのものである。The printed circuit board 3 is formed by depositing a conductive layer 4 made of copper or the like on an insulating plate made of glass epoxy resin or the like by a well-known means.
This is for connecting the semiconductor chip 7 and the lead terminals 2.
このプリント基板３は、接続すべきリード端子２毎に取
付けるため、その形状、大きさは、各リード端子２と接
続する部分及び後述するボンディング可能領域５の所要
面積によって定まる。Since this printed circuit board 3 is attached to each lead terminal 2 to be connected, its shape and size are determined by the portion to be connected to each lead terminal 2 and the required area of a bondable region 5, which will be described later.
又、その厚さは、金属キャップ（図示せず）の高さの関
係上、できるだけ薄くすることが望ましく、例えば１ｍ
ｍ程度とする。In addition, it is desirable to make the thickness as thin as possible due to the height of the metal cap (not shown), for example, 1 m.
It should be about m.
なお、リード端子２が多数ある場合には、複数本毎に１
枚のプリント基板３を取付けることもできる。In addition, if there are many lead terminals 2, one for each
It is also possible to attach two printed circuit boards 3.
導体層４は、上記プリント基板３上面の全部又は一部に
形成され、リード端子２と接続される。The conductor layer 4 is formed on all or part of the upper surface of the printed circuit board 3 and is connected to the lead terminal 2.
又、この導体層４には、後述する半導体チップ７の電極
とワイヤボンディングするためのボンディング可能領域
５が設けられている。Further, this conductor layer 4 is provided with a bondable region 5 for wire bonding to an electrode of a semiconductor chip 7, which will be described later.
このボンディング可能領域５は、金、銀等のワイヤボン
ディング可能な金属を導体層４の一部にメッキすること
により構成される。This bondable area 5 is formed by plating a part of the conductor layer 4 with a wire-bondable metal such as gold or silver.
メッキの厚さは、金の場合は０．５μ汎程度、銀の場合
はこれより厚く数μ肌程度形成される。The thickness of the plating is approximately 0.5 microns in the case of gold, and thicker, approximately several microns, in the case of silver.
なお、このボンディング可能領域５の形成範囲は、上記
のように導体層４の一部だけでなく、第３図及び第４図
に示すように導体層４の全部であってもよい。Note that the formation range of this bondable region 5 is not limited to a part of the conductor layer 4 as described above, but may be the entire conductor layer 4 as shown in FIGS. 3 and 4.
このプリント基板３とリード端子２との接続は、プリン
ト基板３をステム基台１ａ上に載置し、接続すべきリー
ド端子２の先端を、加締め、折曲等により導体層４上に
圧接せしめて行なう。To connect the printed circuit board 3 and the lead terminals 2, the printed circuit board 3 is placed on the stem base 1a, and the tips of the lead terminals 2 to be connected are pressed onto the conductor layer 4 by crimping, bending, etc. I will do it as soon as possible.
又、接続は、導電塗料によって行なうこともできる。Connections can also be made using conductive paint.
なお、第１図乃至第４図に示す実施例では、プリント基
板３に貫通孔３ａを設け、この貫通孔３ａにリード端子
２の先端を挿通させたものであるが、プリント基板に設
けた切欠、プリント基板の外周等にリード端子２を突出
させ、このリード端子２の先端を導体層に圧接させるこ
とも勿論可能である。In the embodiment shown in FIGS. 1 to 4, a through hole 3a is provided in the printed circuit board 3, and the tip of the lead terminal 2 is inserted into this through hole 3a. Of course, it is also possible to make the lead terminals 2 protrude from the outer periphery of the printed circuit board and press the tips of the lead terminals 2 to the conductor layer.
上記半導体チップ７は、シリコン、ゲルマニウム、ガリ
ウム砒素燐等から戊り、ダイオード、トランジスタ等を
構成している。The semiconductor chip 7 is made of silicon, germanium, gallium arsenide phosphorus, etc., and includes diodes, transistors, and the like.
この半導体チップ７は、上記ステム基台１ａ上に導電塗
料等により載置固着される。This semiconductor chip 7 is mounted and fixed on the stem base 1a using conductive paint or the like.
そして、その上面に設けられた電極７ａと上記ボンディ
ング可能領域５とが、金、アルミニウム等の極細金属線
６にてワイヤボンディングされる。Then, the electrode 7a provided on the upper surface and the bondable region 5 are wire-bonded using a very fine metal wire 6 made of gold, aluminum, or the like.
なお、この実施例では、半導体チップ７の各電極７ａを
ワイヤボンディングしているが、第３図及び第４図に示
すように、半導体チップ７の裏面とステム基台１ａとを
直接接続することができる。In this embodiment, each electrode 7a of the semiconductor chip 7 is wire-bonded, but as shown in FIGS. 3 and 4, the back surface of the semiconductor chip 7 and the stem base 1a can be directly connected. Can be done.
又、半導体チップをプリント基板上に載置して、ステム
基台と絶縁することもできる。Alternatively, the semiconductor chip can be placed on a printed circuit board and insulated from the stem base.
以上説明したように、本考案は、リード端子接続用の導
体層を有し且つ該導体層の全部又は一部にボンディング
可能領域を形成して成るプリント基板を介して半導体チ
ップとリード端子とを接続するよう構成することにより
、高価な金、銀をメッキすべき部分を減少してこれらの
使用量を大幅に削減でき、しかも、プリント基板の導体
層にメッキするため、容易に部分メッキができて、手間
がかからず、これによる価格上昇を最小限に抑えること
ができる効果がある。As explained above, the present invention connects a semiconductor chip and lead terminals via a printed circuit board that has a conductor layer for connecting lead terminals and has a bondable area formed in all or part of the conductor layer. By configuring it to connect, it is possible to significantly reduce the amount of expensive gold and silver used by reducing the number of areas that need to be plated.Furthermore, since the conductor layer of the printed circuit board is plated, partial plating is easily possible. This process is time-consuming and has the effect of minimizing price increases.
第１図は本考案半導体素子の一実施例を示す平面図、第
２図は上記第１図のＡ−Ａ断面図、第３図は本考案の他
の実施例を示す平面図、第４図は上記実施例の横断面図
である。
１・・・・・・ステム、２・・・・・・リード端子、３
・・・・・・プリント基板、４・・・・・・導体層、５
・・・・・・ボンディング可能領域、６・・・・・・極
細金属線、７・・・・・・半導体チップ。FIG. 1 is a plan view showing one embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view taken along the line A-A in FIG. The figure is a cross-sectional view of the above embodiment. 1...Stem, 2...Lead terminal, 3
...Printed circuit board, 4...Conductor layer, 5
. . . Bondable area, 6 . . . Ultrafine metal wire, 7 . . . Semiconductor chip.
Claims (1)
該半導体チップの電極の少なくとも一つをリード端子と
ワイヤボンディングして成る半導体素子において、リー
ド端子接続用の導体層を有し且つ該導体層の全部又は一
部にボンディング可能領域を形成して成るプリント基板
を、所定リード端子毎に上記ステム上に載置固着して上
記リード端子と導体層とを接続し、且つ、上記半導体チ
ップの電極とボンディング可能領域とをワイヤボンディ
ングして成ることを特徴とする半導体素子。A semiconductor chip is placed on a stem having lead terminals,
A semiconductor element in which at least one of the electrodes of the semiconductor chip is wire-bonded to a lead terminal, the semiconductor element having a conductor layer for connecting the lead terminal, and a bondable region formed in all or part of the conductor layer. A printed circuit board is placed and fixed on the stem for each predetermined lead terminal to connect the lead terminal and the conductor layer, and the electrode of the semiconductor chip and the bondable area are wire-bonded. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980057332U JPS6032770Y2 (en) | 1980-04-28 | 1980-04-28 | semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980057332U JPS6032770Y2 (en) | 1980-04-28 | 1980-04-28 | semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56161354U JPS56161354U (en) | 1981-12-01 |
| JPS6032770Y2 true JPS6032770Y2 (en) | 1985-09-30 |
Family
ID=29651832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980057332U Expired JPS6032770Y2 (en) | 1980-04-28 | 1980-04-28 | semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6032770Y2 (en) |
-
1980
- 1980-04-28 JP JP1980057332U patent/JPS6032770Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56161354U (en) | 1981-12-01 |
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