JPS61241949A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61241949A JPS61241949A JP60082501A JP8250185A JPS61241949A JP S61241949 A JPS61241949 A JP S61241949A JP 60082501 A JP60082501 A JP 60082501A JP 8250185 A JP8250185 A JP 8250185A JP S61241949 A JPS61241949 A JP S61241949A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- heat
- pellet
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、その実装工程における信鎖
性向上に適用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and relates to a technique that is effective when applied to improve reliability in a mounting process thereof.
半導体装置を電子機器の実装基板へ実装する方法の一つ
に、いわゆる面付方法がある。この方法による実装は、
半導体装置の外部端子を実装基板上の電極に接合材、た
とえば半田で取り付けて行われる。その際、外部端子を
半田熔融温度に加熱することが必要である。One of the methods for mounting a semiconductor device on a mounting board of an electronic device is a so-called surface mounting method. Implementation using this method is
This is done by attaching external terminals of a semiconductor device to electrodes on a mounting board using a bonding material, such as solder. At that time, it is necessary to heat the external terminal to the solder melting temperature.
ところで、上記半導体装置を実装する場合は、外部端子
のみを加熱してやればよい。しかし、外部端子と接合部
が実装基板上面にあるため、たとえば赤外線で加熱して
実装を行う場合には、半導体装置全体に赤外線を照射し
て加熱せざるを得ないことになる。By the way, when mounting the above semiconductor device, it is sufficient to heat only the external terminals. However, since the external terminals and the bonding portion are located on the top surface of the mounting board, for example, when mounting is performed by heating with infrared rays, the entire semiconductor device must be heated by irradiating it with infrared rays.
ところが、上記半導体装置がいわゆるフラットパッケー
ジ型の樹脂封止型半導体装置である場合、実装工程にお
いて実装基板上方からの赤外線照射によりパフケージ上
面が急激に加熱されるため、その熱衝撃によりパフケー
ジにクラック等が発生し、半導体装置の信幀性低下を来
し易いという問題があることが本発明者により見い出さ
れた。However, when the above-mentioned semiconductor device is a so-called flat package type resin-sealed semiconductor device, the top surface of the puff cage is rapidly heated by infrared rays from above the mounting board during the mounting process, and the thermal shock causes cracks etc. in the puff cage. The inventors have discovered that there is a problem in that the reliability of the semiconductor device is likely to deteriorate.
なお、樹脂封止型半導体装置については、１９８０年１
月１５日、株式会社工業調査会発行、日本マイクロエレ
クトロニクス協会Ｉｒｒｃ化実装技術ＪＰ１４９〜Ｐ１
５０に説明されている。Regarding resin-sealed semiconductor devices, the 1980 January
Published by Kogyo Kenkyukai Co., Ltd., Japan Microelectronics Association Irrc Mounting Technology JP149-P1, March 15th
50.
本発明の目的は、面付実装される樹脂封止型半導体装置
の実装時における熱衝撃によるパッケージ破壊等を防止
できる技術を提供することにある。An object of the present invention is to provide a technique that can prevent package breakage due to thermal shock during mounting of a surface-mounted resin-sealed semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、面付実装される樹脂封止型半導体装置につい
て、熱源方向のパッケージ面である実装基板と反対側の
パッケージ表面に熱反射層もしくは膜を被着することに
より、実装工程において熱線照射によるパッケージの加
熱を防止できることにより、該パッケージの急激な温度
変化に伴うパッケージクランク等の発生を有効に防止で
きるものである。In other words, for surface-mounted resin-sealed semiconductor devices, by applying a heat reflective layer or film to the package surface opposite to the mounting substrate, which is the package surface in the direction of the heat source, the package can be heated by heat irradiation during the mounting process. By being able to prevent heating of the package, it is possible to effectively prevent the occurrence of package cranks and the like due to sudden temperature changes in the package.
第１図は本発明による一実施例である半導体装置を第２
図におけるＩ−Ｉ線断面図で示すものであり、第２図は
本実施例の半導体装置の概略平面図である。FIG. 1 shows a second embodiment of a semiconductor device according to the present invention.
This is shown in a sectional view taken along the line II in the figure, and FIG. 2 is a schematic plan view of the semiconductor device of this embodiment.
本実施例の半導体装置は、いわゆるフラットパッケージ
型の樹脂封止型半導体装置であり、エポキシ樹脂１でモ
ールド形成されたパッケージ２のほぼ中央には、ペレッ
ト取付部であるタブ３にペレット４が取り付けられてお
り、該ペレット４のポンディングパッド（図示せず）と
、パッケージ２の側端部に埋設固定されている外部端子
であるリード５の内端部とは、金等のワイヤ６を介して
電気的に接続されている。そして、上記リード５の先端
部５ａは、実装基板７の電極（図示せず）に面付ができ
るように、第１図においてパフケージ下面にほぼ平行に
外側に向かうて折り曲げられている。The semiconductor device of this example is a so-called flat package type resin-sealed semiconductor device, and a pellet 4 is attached to a tab 3 that is a pellet attachment portion approximately in the center of a package 2 molded with an epoxy resin 1. The bonding pad (not shown) of the pellet 4 and the inner end of the lead 5, which is an external terminal embedded in the side end of the package 2, are connected via a wire 6 made of gold or the like. electrically connected. The tip end 5a of the lead 5 is bent outward in a direction substantially parallel to the bottom surface of the puff cage in FIG. 1 so that it can be attached to an electrode (not shown) of the mounting board 7.
本実施例の半導体装置には、そのパッケージの上面に熱
反射膜８が被着されており、また、その一部に非被着部
を設は該被着部９をもって第２図に示すような半導体装
置の識別標識１０が形成されている。In the semiconductor device of this embodiment, a heat reflective film 8 is adhered to the upper surface of the package, and a part of the heat reflecting film 8 is provided with a non-adhered portion as shown in FIG. A semiconductor device identification mark 10 is formed.
上記該熱反射膜は、エポキシ樹脂等にアルミニウム微粉
末を含有せしめて塗料としたものを用いて印刷塗布し、
その後熱硬化を行わせることにより被着形成できる。こ
のように印刷方法を採用することにより、任意の識別標
識を容易に形成することができるものである。The above-mentioned heat-reflecting film is printed and coated using a paint made by containing fine aluminum powder in epoxy resin, etc.
Adhesion can then be formed by thermal curing. By employing this printing method, any identification mark can be easily formed.
ところで、通常のフラットパッケージ型の半導体装置は
、実装基板７にリード先端部５ａを半田で接合する場合
に、該半導体装置の上方に位置する赤外線ランプ（図示
せず）から赤外線を照射してリード先端部５ａを半田熔
融温度以上に加熱する必要がある。By the way, in a normal flat package type semiconductor device, when the lead tips 5a are soldered to the mounting board 7, the leads are irradiated with infrared rays from an infrared lamp (not shown) located above the semiconductor device. It is necessary to heat the tip 5a to a temperature higher than the solder melting temperature.
その際の赤外線は、赤外線ランプ方向の半導体装置の全
体に照射されるため、パッケージ２自体も急激に昇温さ
れることになる。そのため、熱衝撃によりパッケージク
ランク、パッケージ樹脂とリードとの剥がれ等の種々の
欠陥が発生することになる。Since the infrared rays at this time are irradiated onto the entire semiconductor device in the direction of the infrared lamp, the temperature of the package 2 itself is also rapidly increased. Therefore, thermal shock causes various defects such as peeling of the package crank and the package resin from the leads.
本実施例の半導体装置においては、赤外線等の熱線を有
効に反射する熱反射膜が熱源側のパッケージ表面に形成
されているため、上記実装工程におけるパッケージの熱
衝撃を防止できる。したがって、半導体装置の信鯨性低
下を来すパッケージクランク等の発生をも有効に防止で
きるものである。In the semiconductor device of this embodiment, a heat reflective film that effectively reflects heat rays such as infrared rays is formed on the surface of the package on the heat source side, so that thermal shock to the package in the above-mentioned mounting process can be prevented. Therefore, it is possible to effectively prevent the occurrence of package cranks, etc., which cause a decrease in reliability of the semiconductor device.
また、パッケージ上面全体に熱反射膜を形成すると別に
半導体装置の識別標識を付着する工程が必要となるが、
前記の如く一部非被着部を識別標識として利用すること
により、熱反射膜の形成と識別標識の形成とを同時に一
工程で達成できる利点もある。Additionally, forming a heat reflective film on the entire top surface of the package requires a separate process to attach an identification mark for the semiconductor device.
As described above, by using the partially unattached portion as an identification mark, there is an advantage that the formation of the heat reflective film and the formation of the identification mark can be accomplished simultaneously in one step.
（１）１面付実装される樹脂封止型半導体装置について
、実装面と反対側のパッケージ表面に熱反射膜を被着す
ることにより、実装工程における熱源から照射される熱
線をパッケージ表面で反射できるので、パッケージ自体
が熱衝撃を受けることなく半導体装置を実装できる。(1) For resin-sealed semiconductor devices that are mounted on one side, by applying a heat reflective film to the package surface opposite to the mounting surface, the package surface reflects the heat rays emitted from the heat source during the mounting process. Therefore, semiconductor devices can be mounted without the package itself being subjected to thermal shock.
（２）、前記＋１１により、熱衝撃に起因するパッケー
ジクランク等の発生を防止できるので、実装後の半導体
装置についてその信顛性向上を達成できる。(2) The +11 described above makes it possible to prevent the occurrence of package cranks caused by thermal shock, thereby improving the reliability of the semiconductor device after mounting.
（３）、熱反射膜を印刷法で被着形成する場合、一部に
非被着部を形成することにより、該被着部からなる識別
標識を同時に形成できる。(3) When a heat reflective film is deposited by a printing method, by forming a non-deposited part in a part, an identification mark made of the deposited part can be formed at the same time.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではな（、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples (although it is possible to make various changes without departing from the gist of the invention). Not even.
たとえば、熱反射膜としてはアルミニウム微粉末を含有
したエポキシ樹脂等からなる塗料を塗布して形成するも
のについて説明したが、これに限るものでなく他の金属
またはチタン白等の白色顔料を含有してもよく、また樹
脂もエポキシ樹脂に限るものでない。For example, although we have described a heat-reflecting film formed by applying a paint made of epoxy resin containing fine aluminum powder, it is not limited to this, and may contain other metals or white pigments such as titanium white. Also, the resin is not limited to epoxy resin.
さらには、印刷法によるものに限らず、金属自体を蒸着
等で被着してもよい。Furthermore, the metal itself may be deposited by vapor deposition or the like, without being limited to the printing method.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である、いわゆるフラット
パッケージ型の半導体装置に適用した場合について説明
したが、それに限定されるものではなく、たとえば、い
わゆるＰＬＣＣ型またはｓｏｐ型等の面付実装される樹
脂封止型半導体装置についても適用してを効な技術であ
る。In the above explanation, the invention made by the present inventor was mainly applied to the so-called flat package type semiconductor device, which is the background field of application, but the present invention is not limited thereto. This technique is also effective when applied to surface-mounted resin-sealed semiconductor devices such as PLCC type or SOP type.
第１図は本発明による一実施例である半導体装置を示す
第２図における１−１線断面図、第２図は本実施例の半
導体装置の概略平面図である。
１・・・エポキシ樹脂、２・・・パフケージ、３・・・
タブ、４・・・ペレット、５・・・ＩＪ ＋ド、５ａ・
・・先端部、６・・・ワイヤ、７・・・実装基板、８・
・・熱反射膜、９・・・被着部、１０・・・識別標識。
第 １ 図
第 ２ 図FIG. 1 is a sectional view taken along line 1-1 in FIG. 2 showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic plan view of the semiconductor device of this embodiment. 1... Epoxy resin, 2... Puff cage, 3...
Tab, 4...Pellet, 5...IJ+do, 5a・
・Tip part, 6... Wire, 7... Mounting board, 8...
... Heat reflective film, 9 ... Adhesive part, 10 ... Identification mark. Figure 1 Figure 2
Claims (1)
装基板と反対側のパッケージ表面に熱反射層が形成され
てなる半導体装置。 ２、半導体装置の識別記号が熱反射層の非存在部によっ
て表示されていることを特徴とする特許請求の範囲第１
項記載の半導体装置。 ３、熱反射層が熱反射性顔料を含有する塗料から形成さ
れていることを特徴とする特許請求の範囲第１項記載の
半導体装置。 ４、熱反射性顔料が金属微粉末または白色顔料であるこ
とを特徴とする特許請求の範囲第３項記載の半導体装置
。 ５、熱反射層が蒸着金属によって形成されていることを
特徴とする特許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. A resin-sealed semiconductor device that is surface-mounted and has a heat reflective layer formed on the surface of the package opposite to the mounting substrate. 2. Claim 1, characterized in that the identification symbol of the semiconductor device is displayed by a portion where the heat reflective layer does not exist.
1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1, wherein the heat reflective layer is formed from a paint containing a heat reflective pigment. 4. The semiconductor device according to claim 3, wherein the heat reflective pigment is a fine metal powder or a white pigment. 5. The semiconductor device according to claim 1, wherein the heat reflective layer is formed of a vapor-deposited metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60082501A JPS61241949A (en) | 1985-04-19 | 1985-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60082501A JPS61241949A (en) | 1985-04-19 | 1985-04-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61241949A true JPS61241949A (en) | 1986-10-28 |
Family
ID=13776245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60082501A Pending JPS61241949A (en) | 1985-04-19 | 1985-04-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61241949A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2620275A1 (en) * | 1987-09-04 | 1989-03-10 | Thomson Hybrides Microondes | Case for the surface mounting of a component operating at radio frequency |
| US5184208A (en) * | 1987-06-30 | 1993-02-02 | Hitachi, Ltd. | Semiconductor device |
| US5365113A (en) * | 1987-06-30 | 1994-11-15 | Hitachi, Ltd. | Semiconductor device |
| AU695731B2 (en) * | 1995-06-21 | 1998-08-20 | Illinois Tool Works Inc. | Infrared shield for capacitors |
-
1985
- 1985-04-19 JP JP60082501A patent/JPS61241949A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184208A (en) * | 1987-06-30 | 1993-02-02 | Hitachi, Ltd. | Semiconductor device |
| US5365113A (en) * | 1987-06-30 | 1994-11-15 | Hitachi, Ltd. | Semiconductor device |
| US5514905A (en) * | 1987-06-30 | 1996-05-07 | Hitachi, Ltd. | Semiconductor device |
| US5742101A (en) * | 1987-06-30 | 1998-04-21 | Hitachi, Ltd. | Semiconductor device |
| FR2620275A1 (en) * | 1987-09-04 | 1989-03-10 | Thomson Hybrides Microondes | Case for the surface mounting of a component operating at radio frequency |
| AU695731B2 (en) * | 1995-06-21 | 1998-08-20 | Illinois Tool Works Inc. | Infrared shield for capacitors |
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