JPS59195850A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59195850A
JPS59195850A JP6958183A JP6958183A JPS59195850A JP S59195850 A JPS59195850 A JP S59195850A JP 6958183 A JP6958183 A JP 6958183A JP 6958183 A JP6958183 A JP 6958183A JP S59195850 A JPS59195850 A JP S59195850A
Authority
JP
Japan
Prior art keywords
cap
chip
semiconductor device
metal cap
multilayer substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6958183A
Other languages
Japanese (ja)
Inventor
Atsushi Nakazawa
淳 中澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6958183A priority Critical patent/JPS59195850A/en
Publication of JPS59195850A publication Critical patent/JPS59195850A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To obtain the semiconductor device having a high humidity resistance and a long-term reliability by covering the periphery of chip parts soldered onto a multilayer substrate such as a chip carrier and a chip condenser with a cap which is filled with curing filler. CONSTITUTION:For a chip carrier 2, a cap 7 made of plastic is stuck to a multilayer substrate 1 in N2 gas 8 atmosphere to form a protective coating and the periphery of these is covered with curing epoxy resin 10, which is crowned with a metal cap 9 made of brass or Al. After crowning with the metal cap 9, a metallic covering member 11 crowns said metal cap 9 by welding with laser beam in order to prevent an invasion of humidity from the upper part where the epoxy resin 10 is exposed. Meanwhile, a projecting part of a lead 4 is fixed by a non-conductive adhesive 12 in order to prevent a short with the metal cap 9.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は半導体デバイスに係り、特にシングル・イン・
ライン・パッケージ(S ingle −in −1i
ne  pacltage、以下SIPと略記する)形
半導体デバイスに関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a single-in semiconductor device.
Line package (Single-in-1i)
ne pacltage (hereinafter abbreviated as SIP) type semiconductor device.

[発明の技術的背景] 従来のSIP形半導体デバイスは、第1図に示すように
、ICメモリー等のチップキャリア2およびチップコン
デンサ3等のチップ部品をセラミック等からなる多層基
板]上に直接半日付けして構成されでいた。
[Technical Background of the Invention] As shown in FIG. 1, a conventional SIP type semiconductor device is manufactured by directly mounting chip components such as a chip carrier 2 such as an IC memory and a chip capacitor 3 on a multilayer substrate made of ceramic or the like. It was configured by attaching it.

[背景技術の問題点] しかるに、このような従来のSIP形半導体デバイスぐ
は、チップキャリア2およびチップコンデンザ3等のチ
ップ部品が直接多層基板1上に半田付けされているだけ
ぐあるため、例えば熱衝撃試験、耐湿性試験、高温放置
試験、温度サイクル試験等の一般的な環境試験を行なっ
た場合に多層基板1とチップキャリア2およびチップコ
ンデンtl−3Wのチップ部品との間の半田付は部分が
劣化し、チップ部品が多層基板1から取れ易く、またチ
ップ部品の特性が急激に劣化し易いという欠点があった
[Problems with Background Art] However, in such conventional SIP type semiconductor devices, chip components such as the chip carrier 2 and the chip capacitor 3 are directly soldered onto the multilayer substrate 1; For example, when general environmental tests such as thermal shock tests, moisture resistance tests, high-temperature storage tests, and temperature cycle tests are performed, soldering between the multilayer board 1 and the chip components of the chip carrier 2 and chip capacitor TL-3W However, there are disadvantages in that parts deteriorate, the chip components tend to come off from the multilayer substrate 1, and the characteristics of the chip components tend to deteriorate rapidly.

「発明の目的J 本発明はこのような欠点を解決するためになされたもの
で、耐湿性が強く長期的信頼性のある半導体デバイスを
提供することを目的とする。
``Object of the Invention J The present invention was made to solve these drawbacks, and an object thereof is to provide a semiconductor device that is highly moisture resistant and has long-term reliability.

[発明の概要J すなわち本発明は、セラミック等からなる多層基板上に
チップキャリア、チップコンデンサ等のチップ部品を半
田付けしでなる半導体デバイスにおいて、多層基板上に
半田付けされたチップキャリア、チップコンデンサ等の
チップ部品の外周を岑ヤツプで覆い、このキャップ内に
硬化性4充填剤を充填してなることを特徴とする半導体
デバイスである。
[Summary of the Invention J That is, the present invention relates to a semiconductor device in which chip components such as a chip carrier and a chip capacitor are soldered onto a multilayer substrate made of ceramic or the like. This semiconductor device is characterized in that the outer periphery of a chip component such as the above is covered with a cap, and the cap is filled with a hardening 4 filler.

[発明の実施例] 以下本発明の詳細を図面に示ターー実施例について説明
する。
[Embodiments of the Invention] The details of the present invention will be described below with reference to the drawings and embodiments.

第2図は本発明になる半導体デバイスの一実施例を示す
断面図である。図において符号1はセラミック等からな
る多層基板であり、この多層基板上にICメモリー等の
チップキャリア2が半田付けされ、このチップキャリア
2と電極5とが25μないし30μの直径のAuワイヤ
6によりボンディングされている。また、図示しないチ
ップコンデンサ等の他のチップ部品も多層基板1上に半
田付けされている。前記チップキャリア2に対しては、
N2ガス8雰囲気中でプラスチック製のキt・ツブ7を
多層基板1に接着して保護被覆を形成し、かつその周囲
を硬化性のエポキシ樹脂10で充填し、その外部にしん
ちゅう又はアルミ等からなる金属製キャップ9を冠着す
る。この金属製キレツブ9を冠着した後に、上面のエポ
キシ樹脂10が露出した部分から湿気が侵入することを
防ぐために、金FA製蓋体11をレーザー光線により前
記金属製キャップ9に溶接し冠着する。
FIG. 2 is a sectional view showing an embodiment of the semiconductor device according to the present invention. In the figure, reference numeral 1 denotes a multilayer board made of ceramic or the like, and a chip carrier 2 such as an IC memory is soldered onto this multilayer board, and the chip carrier 2 and electrodes 5 are connected by Au wires 6 with a diameter of 25μ to 30μ. It is bonded. Other chip components such as chip capacitors (not shown) are also soldered onto the multilayer substrate 1. For the chip carrier 2,
A plastic kit 7 is bonded to the multilayer substrate 1 in an atmosphere of N2 gas 8 to form a protective coating, and its surroundings are filled with hardening epoxy resin 10, and the outside is covered with brass, aluminum, etc. A metal cap 9 made of is attached. After this metal cap 9 is capped, a gold FA lid 11 is welded to the metal cap 9 using a laser beam to prevent moisture from entering through the exposed portion of the epoxy resin 10 on the top surface. .

一方、リード4の突出部は金属製主11ツブ9とのショ
ートを防ぐl〔めに非導電性接着剤12で固定する。こ
のように1)でチップキャリア2とチップコンデンサ等
のチップ部品が金属製キャップ9、金属製蓋体11中に
完全に密封され耐湿性の強い半導体デバイスが得られる
On the other hand, the protruding portion of the lead 4 is fixed with a non-conductive adhesive 12 to prevent short-circuiting with the metal main 11 knob 9. In this way, in step 1), the chip carrier 2 and the chip components such as the chip capacitor are completely sealed in the metal cap 9 and the metal lid 11, and a highly moisture-resistant semiconductor device is obtained.

第3図は本発明になる半導体デバイスの他の実施例であ
り、第2図の実施例と異なり、二VVツブ7を用いず、
シリコーン13をチップコンデンサ2等のチップ部品上
にボッティングし構成したものである。
FIG. 3 shows another embodiment of the semiconductor device according to the present invention, which differs from the embodiment in FIG.
It is constructed by botting silicone 13 onto a chip component such as a chip capacitor 2.

本実施例の他の構成部分は、第2図の実施例と同一であ
るので、その説明を省略する。
The other constituent parts of this embodiment are the same as those of the embodiment shown in FIG. 2, so their explanation will be omitted.

第4図は本発明になる半導体デバイスの第3の実施例を
示す断面図である。本実施例においては、多層基板1の
メタライズ部1aにコバールまたは42Fe/Ni合金
からなる金属製キャップ9aをレーザー光線により溶接
し、多層基板1上に直接封止するものである。本実施例
の他の構成部分は第2図の実施例と同一であるので、そ
の説明を省略する。
FIG. 4 is a sectional view showing a third embodiment of the semiconductor device according to the present invention. In this embodiment, a metal cap 9a made of Kovar or 42Fe/Ni alloy is welded to the metallized portion 1a of the multilayer substrate 1 using a laser beam, and is directly sealed onto the multilayer substrate 1. The other components of this embodiment are the same as those of the embodiment shown in FIG. 2, so their explanation will be omitted.

[発明の効果] 以上述べたように本発明になる半導体デバイスにおいC
は、チップキャリア等のチップ部品の外周をキャップで
覆い、このキャップ内に硬化性充填剤を充填して構成し
たのぐ、耐湿性に優れ、長期的に高い信頼性が得られる
[Effect of the invention] As described above, in the semiconductor device of the present invention, C
By covering the outer periphery of a chip component such as a chip carrier with a cap and filling the cap with a curable filler, the cap has excellent moisture resistance and high long-term reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体デバイスを示す斜視図、第2図は
本発明の一実施例を示す断面図、第3図は本発明の伯の
実施例を示ず断面図、第4図は本発明の第3の実施例を
示す断面図である。 1・・・・・・・・・・・・多層基板 2・・・・・・・・・・・・チップキャリア3・・・・
・・・・・・・・チップコンデンサ4・・・・・・・・
・・・・リード 7・・・・・・・・・・・・キャップ 8・・・・・・・・・・・・N2ガス 9.9a・・・金属製キャップ 10・・・・・・・・・・・・充填剤 11・・・・・・・・・・・・金属製蓋体12・・・・
・・・・・・・・非導電性接着剤13・・・・・・・・
・・・・シリコーン代理人弁理士   須 山 仏 − 第1図 第2図 第3図 第4図
FIG. 1 is a perspective view showing a conventional semiconductor device, FIG. 2 is a cross-sectional view showing an embodiment of the present invention, FIG. 3 is a cross-sectional view showing an embodiment of the present invention, and FIG. FIG. 7 is a sectional view showing a third embodiment of the invention. 1...Multilayer board 2...Chip carrier 3...
・・・・・・・・・Chip capacitor 4・・・・・・・・・
...Lead 7...Cap 8...N2 gas 9.9a...Metal cap 10... ......Filler 11...Metal lid body 12...
......Non-conductive adhesive 13...
...Silicone patent attorney Suyama Buddha - Figure 1 Figure 2 Figure 3 Figure 4

Claims (6)

【特許請求の範囲】[Claims] (1)セラミック等からなる多層基板上にチップキャリ
ア、チップコンデンサ等のチップ部品を半田付けしてな
る半導体デバイスにおいて、多層基板上に半田付けされ
たチップキャリア、チップコンデンサ等のチップ部品の
外周をキャップで覆い、このギャップ内に硬化性充填剤
を充填してなることを特徴とする半導体デバイス。
(1) In semiconductor devices in which chip parts such as chip carriers and chip capacitors are soldered onto a multilayer board made of ceramic etc., the outer periphery of the chip parts such as chip carriers and chip capacitors soldered onto the multilayer board is A semiconductor device characterized by being covered with a cap and filling the gap with a curable filler.
(2)キャップの内側となるチップ部品の外周には保護
被覆が設けられ、硬化性充填剤はキャップと保護被覆間
に充填される特許請求の範囲第1項記載の半導体デバイ
ス。
(2) The semiconductor device according to claim 1, wherein a protective coating is provided on the outer periphery of the chip component that is inside the cap, and the curable filler is filled between the cap and the protective coating.
(3)保護被覆はプラスチック製のキャップである特許
請求の範囲第2項記載の半導体デバイス。
(3) The semiconductor device according to claim 2, wherein the protective covering is a plastic cap.
(4)保護被覆はシリコーンボッディング層である特許
請求の範囲第2項記載の半導体デバイス。
(4) The semiconductor device according to claim 2, wherein the protective coating is a silicone bodding layer.
(5)キャップは金属製キャップである特許請求の範囲
第1項ないし第4項のいずれか1項記載の半導体デバイ
ス。
(5) The semiconductor device according to any one of claims 1 to 4, wherein the cap is a metal cap.
(6)金属製キャップの開口部は金属製蓋体もしくは多
層基板により覆われ、レーザー光線により溶接され封止
されている特許請求の範囲第5項記載の半導体デバイス
(6) The semiconductor device according to claim 5, wherein the opening of the metal cap is covered with a metal lid or a multilayer substrate and sealed by welding with a laser beam.
JP6958183A 1983-04-20 1983-04-20 Semiconductor device Pending JPS59195850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6958183A JPS59195850A (en) 1983-04-20 1983-04-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6958183A JPS59195850A (en) 1983-04-20 1983-04-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59195850A true JPS59195850A (en) 1984-11-07

Family

ID=13406915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6958183A Pending JPS59195850A (en) 1983-04-20 1983-04-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59195850A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
US5392197A (en) * 1991-09-03 1995-02-21 Robert Bosch Gmbh Moisture proof of electric device for motor vehicles
US5814882A (en) * 1994-07-20 1998-09-29 Nec Corporation Seal structure for tape carrier package
JP2013172093A (en) * 2012-02-22 2013-09-02 Denso Corp Semiconductor device and manufacturing method of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
US5392197A (en) * 1991-09-03 1995-02-21 Robert Bosch Gmbh Moisture proof of electric device for motor vehicles
US5814882A (en) * 1994-07-20 1998-09-29 Nec Corporation Seal structure for tape carrier package
JP2013172093A (en) * 2012-02-22 2013-09-02 Denso Corp Semiconductor device and manufacturing method of the same

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