JPS58136151A - Error correction system - Google Patents

Abstract

PURPOSE:To eliminate a parity error due to a fixed obstacle of a transfer path, by transferring inverted data at retrial. CONSTITUTION:Data inverting circuits 4, 5 invert all input data and output them when a retrial request (c) is set. If a fixed obstacle of 1-bit, binary 0 clamped to a data of the transfer path takes place, since the obstacle is 0 at a parity check circuit 2, a parity error is displayed. In this case, the parity check circuit 2 sets the request (c) and a retrial control circuit 3 inputs the retrial data to the circuit 4. This data is propagated in a transfer path 10, inverted again at the circuit 5 and inputted to the circuit 2. That is, when the input of the circuit 2 is binary 1, even if the fixed obstacle clamped to binary 0 in the transfer path 10 takes place, the data is inputted to the circuit 5 without being subject to the clamped fixed obstacle, and the data is inverted at the circuit 5, binary 1 is inputted to the circuit 2, allowing to eliminate a parity check error.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transfer device that has a parity check function and is capable of retry processing.

Conventionally, this lumber transfer device includes a parity generation circuit that generates data parity, a parity check circuit, and a retry control circuit.

To explain the conventional device in detail with reference to the drawings,
FIG. 1 is a block diagram showing an example of a conventional device of this type.

In FIG. 1, the sending data is sent to the parity generation circuit l#! via the signal line a. ! / and is sent to the node generation circuit l
It is sent to the subsequent stage and the parity check circuit together with the parity bit (signal line b) generated in . The parity check circuit checks the transferred data and parity, and sends a message to the retry control circuit 3 via the retry request signal line C when retry processing is possible due to a temporary retrieval error.
request a retry. IJ) In response to the retry request, the write control circuit 3 sends the data in which the parity error has occurred again to the subsequent stage and the parity check circuit.

However, the conventional configuration has the drawback that a parity error occurs even if data is transferred again in a retry on a transfer path where a fixed failure has occurred.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the prior art, and therefore, it is an object of the present invention to solve the problem of parity error when a fixed failure occurs in the forwarding path, such as a forward failure or an failure. An object of the present invention is to provide a new data transfer method that makes it possible to transfer data without causing a parity error by inverting and transmitting temporary data.

The above-mentioned object of the present invention is to provide a data inversion circuit for inverting data to be retransmitted to the transmitting side when retry processing is possible at the time of parity error, in a transfer device having a parity check function and capable of retry processing at the time of parity error. ,
This is achieved by a patented data transfer device in which a data inverting circuit for returning the data to the original data is provided on the receiving side.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

In FIG. 2, which shows an embodiment of the present invention, the operations of the parity generation circuit, parity check circuit, and reply control circuit 3 are similar to those of the conventional device shown in FIG. The data inversion circuit tei, j has a function of inverting all the input data and outputting it when the retry request signal C is set, and outputting the input data as is when the retry amazine signal C is not set.

Here, the data with the transfer path has 7 bits, -adc@O'
When a fixed fault occurs that is clamped to ``, a parity error occurs because the data that should originally be ``/'' becomes 10'' in the parity check circuit. sets retry request signal line C, and in response to this, retry control circuit JF
The i retry data is sent from the signal line a and is input to the data inversion circuit. On the other hand, the data inversion circuit is IJ)
When the retry request signal C is set, all the input data is inverted, so the retry data is sent to the transfer path/in an inverted form.
θ is propagated, the MU is inverted by the data inverting circuit S, and the signal is input to the parity check circuit. That is, when the input to the retry control circuit 30 is co-progressive °l'', 2 is applied to the transfer path lθ.
Even if there is a fixed fault that clamps the
In the transfer path 10, since the data is inverted, the
Since `` is the correct value, the data is input to the data inverting circuit without suffering from the @θ'' clamp fixing failure, where it is successfully inverted and the co-digital ``/'' is input to the parity check circuit to perform the parity check. Errors can be avoided.

As explained above, the present invention can avoid parity errors caused by fixed failures in the transfer path by transferring inverted data at the time of retry, and by using data after retry instead of data before retry. It has the effect of correcting mistakes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional device, and FIG. 1 is a block diagram showing an embodiment of the present invention. l...Parity generation circuit, -...Parity check circuit, 3...Read 2i control circuit %"l'...Data inversion circuit, a...Transfer data signal line, b...Parity Pit signal line, C...IJ) Raisui signal line, d
, e...Data line line. Patent applicant: NEC Corporation Representative: Patent attorney Yutabe Kumagai

Claims (1)

[Claims] In an information processing device that has a parity check function and is capable of retry processing that sends out data that has a parity error at one time, a data inversion circuit is provided on both the transmitting and receiving sides, and data inverted at the time of retry is sent out, and the receiving side An error correction method characterized by inverting the data again and performing a parity check.