JPH02266728A - Data transmission error control system - Google Patents

Abstract

PURPOSE:To perform data transfer normally even when a fixed fault occurs by taking the ENOR of data received first and the data received in the first re-transmission, and repeating the combinational transmission of bits that go to '1'. CONSTITUTION:A processor A compares return data from a processor B with original data, and performs the recursive transmission of the data in which all bits are inverted when noncoincidence is obtained. When the noncoincidence is obtained in second data comparison, the processor B takes the ENOR (inversion of exclusive OR) of first reception data and second reception data (inversion data), and detects a defective data part. When the defective data part is detected, the data is transferred to the processor A with the combination of ON ('1') and OFF ('0') possibly considered for the defective part, and comparison with the original data is performed at a processor A side. Such sequence is repeated until coincidence between both data can be obtained. Thereby, it is possible to perform the data transfer normally even when the fixed data fault occurs.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data transmission error control method when transmitting data between processors, more specifically, regarding a data transmission error control method when transmitting and receiving data using a repeated transmission method. The purpose of this system is to enable normal data transfer between processors even when a transmission failure occurs. Data is transferred from processor A to processor B, and processor B transfers the received data to processor A. Processor A reads the data returned from Processor B in the sending state and compares it with the original data. If a mismatch occurs, Processor A inverts all bits of the data and transfers it to Processor B. Processor B then returns the received retransmitted data as is to processor A. Processor A compares the returned data with the retransmitted data, and if a mismatch occurs,
Processor A transfers the original data to processor B again, and processor B performs ENOR between the first received data and the first retransmitted data, finds the bit that is 1, and transfers the data to processor B. For the received data, change the corresponding bits of the received data to the bit pattern obtained by the combination of on/off of this bit and send it back, and in step 8, processor A side sends the combination of bits that are ENOR'd and become 1. The configuration is such that it is repeated until the sent data and returned data match.

[Industrial Application Field] The present invention relates to a data transmission error control method when transmitting data between processors, and more particularly to a data transmission error control method when transmitting and receiving data using a repetitive transmission method.

When data is transmitted between processors, it is necessary to check whether the data has been transmitted correctly, and various data transmission error detection methods are used for this purpose. This data transmission error detection needs to be accurate and reliable.

[Prior Art J] When transmitting data between processors, there is a repeated transmission method as a method for checking whether data transmission has been performed accurately. FIG. 8 is an explanatory diagram of a conventional repetitive transmission system. Processor A has data holding register IA
, a data storage buffer memory 2A, and a control program (specifically, a CPU) 3A that controls these registers IA and buffer memory 2A, and processor B also has a similar register IB and buffer memory 2B.
and a control program 3B.

Now, assume that processor A transfers data stored in buffer memory 2A to processor B. The data stored in the buffer memory 2A is sequentially read out by the control program 3A, enters the register IA, and is transferred from the register IA to the processor B. 9th
Figure (A) is a diagram showing the state of data transfer. From processor A to processor B, a, b, c, d, etc.
・Data is transferred in the order of . Processor B sequentially stores the received data in buffer memory 2b under the control of control program 3B. When processor A completes all data transfer, processor A notifies processor B to that effect.

Upon receiving the notification, processor B stores buffer memory 2.
Sequentially read the data stored in B and register IB.
The data are sent back to processor A in the order in which they are received. FIG. 9(b) shows the order in which data is returned from processor B to processor A, in the order in which it was received, that is, a, b,
The order is c, d... Processor A compares the returned data with the original data stored in buffer memory 2A to check whether the data has been transmitted correctly. If all the data match, it is known that the data transmission from processor A to processor B was performed normally.

[Problems to be Solved by the Invention] In the conventional repetitive transmission method described above, there is no problem if all data transmission is successful, but if there is a discrepancy between the original data and the returned data on the processor A side. It becomes a problem if it occurs. In other words, if a mismatch occurs, all data is retransmitted from processor A to processor B from the beginning. In such a system, the sequence of retransmission of the same data from processor A -> retransmission of received data from processor B -> data matching detection on the processor A side is repeated until the data match. However, in such a system, if a fixed transmission failure occurs, normal data transfer cannot be performed no matter how many times the data is retransmitted.

As a result, there was a problem in that data transfer was impossible.

The present invention has been made in view of these problems, and provides a data transmission error control method that allows data transmission between processors to be performed normally even when a fixed transmission failure occurs. It is intended to.

[Means for Solving the Problems] FIG. 1 is a flowchart showing the principle of the system of the present invention. The present invention provides a method for transmitting data from processor A to processor B when processor A and processor B are connected via a data register and a control register, and data is transmitted between processor A and processor 8 using a control program. (Step 1), Processor B sends the received data back to Processor A (Step 2), and Processor A reads the data returned from Processor B in the sending state and compares it with the original data (Step 3). ), if a mismatch occurs, processor A inverts all bits of the data and resends it to processor B (step 4).
, Processor B sends the received retransmitted data back to processor A as is (Step 5). Processor A compares the returned data with the retransmitted data (Step 6), and if a mismatch occurs, Processor A transfers the original data to processor B again (Step 7)
, Processor B performs ENOR between the first received data and the first retransmitted data, finds the bit that is 1, and applies the obtained bit to the retransmitted data by turning on and off this bit. Change the corresponding bit of the received data to the bit pattern and send it back (Step 8), and send the combination of the bits that were ENORed to 1 in Step 8 until the processor A matches the sent data and the returned data. It is characterized in that it is configured to repeat (step 9).

[Operation] The data returned from processor B is compared with the original data using the repetitive transmission method, and if a discrepancy occurs, the next data with all pits inverted is repeatedly transmitted. If there is a mismatch in the second data comparison, processor B performs ENOR (exclusive OR inversion) between the first received data and the second received data (in this case, inverted data). Detect bad data parts. When a defective data part is detected, data is transferred from processor B to processor A for this defective part using possible combinations of ON (“1°”) and OFF (“0”), and processor A side combines the data with the original data. This sequence is repeated until both data match.

By adopting such a configuration, normal data transmission can always be performed even if there is a fixed data failure.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of a computer system to which the present invention is applied. In the figure, processor A includes a data register 11A that holds data for transmission, and a control register 1 that holds data for mutually notifying each other of determining write mode or read mode, securing priority, etc.
2A, a buffer memory 13A in which transfer data is stored, and a control program 14A that controls data transmission. This configuration is the same on the processor B side, including a data register 11B, a control register 12B, a buffer memory 13B, and a control program 14.
It is composed of B. Control programs 14A, 14B
Specifically, it is a CPU (not shown) that operates the .

In the system configured as described above, notification of priority reservation is sent from control registers 12A to 12B,
Assume that data is transferred from processor A to processor B. At this time, the data stored in the buffer memory 13A is transferred to the processor B side via the data register 11A under the control of the control program 14A. At the same time, processor B sends the received data back to processor A via data register IIB.

On the processor A side, the returned data is successively compared with the original data stored in the buffer memory 13A while remaining in the transmission state. As a result of the comparison, if both data match, the #l111 program 14A stores the next data to be transmitted in the buffer memory 13A for the next data transmission.
Data is transferred by reading from and writing to data register IIA.

If mismatched data is generated as a result of the comparison, the control register 12A notifies the control register 12B of the mismatch. Then, the control program 14A inverts all bits of the data, sets it in the data register IIA, and retransmits it to the processor B. When processor B receives the inverted data via data register 11B, processor B returns the received data to processor A as is. On the processor A side, the returned data is compared with retransmitted data (inverted data of the original data).

If a mismatch occurs after comparing the returned data and the retransmitted data, the control register 12A notifies the control register 12B of the mismatch. And sr.
The s program 14A again reads the original data (data before being inverted) from the buffer memory 13A, sets it in the data register 11A, and transfers it to the processor B.

The processor Bg14 receives the data from the processor A, performs an ENOR operation on the data first received by the control program 14B, and the data received at the first retransmission, and finds the bit for which the result is '1'. , change the corresponding bit of the received data to the bit pattern obtained by the combination of on/off of this bit (the bit where @1" is set) for the retransmitted data, set it in the data register 11B, and processor A send it back to

On the processor A side, the data sent from processor B is compared with the original transmitted data. As a result of the comparison, if there is a mismatch, a notification is sent to the processor B side via the control register 12A.

As a result, on the processor B side, the control program 14B stores the next bit pattern combination in the data register 11B.
, and sends it back to processor A. On the processor A side, the control program 14A compares the sent data with the original data.

This sequence is repeated until both data match. According to the method of the present invention, no matter how many transmission failure bits there are, by repeating the comparison sequence, they always match. If they match, that data is the first data transferred from processor A to processor B. If they match, processor A notifies processor B of the match via control register 12A. When processor B receives this match notification,
The data is stored in the buffer memory 13B.

FIG. 3 is a diagram showing a detailed configuration example of an embodiment of a computer system to which the present invention is applied. The same thing as in Figure 2 is
Indicated with the same reference numerals. The figure shows the control registers 12A and 12B in detail. For example, regarding the processor A side, when sending control information from processor A to processor B (at the time of writing), the control register 12A1 is used;
When receiving control information such as h1 (at the time of reading), the control register 12A2 is used.

Control register 12A1 has RQSND bit, R
It consists of TSND bit, FR8T bit and RSTDT bit. This control register 12A
1 is used at the time of writing, and the meaning of each constituent bit is as shown in FIG. Control register 12A2 has SND bit, RCV pin, BUSY
It consists of bits (Beep) and DTRDY. This control register 12A2 is used at the time of reading, and the meaning of each constituent bit is as shown in FIG.

The RQSND bit requests a transmission right by writing "1" when performing data transfer.

When this transmission request is accepted, the SND bit becomes "1" when this register 12A1 is read, and the RCV bit on the other side becomes "1".The RTSND bit is set to "1" when the data transfer is completed, and the transmission is transmitted. When the transmission right is released, when reading this register 12A1, S
The ND bit becomes “0” and the RCV bit of the other party becomes “0”.
It becomes Oo.

The FR3T bit is written with “1°” when data transmission is forcibly interrupted to perform error control.

With this operation, all bits of this register 12A1 are set to “
0", and the other party is in the same state. R8
The TDT bit is set to DTR when reading this register 12A1.
By writing "1" to this bit when the DY bit is '1m', the DTRDY bit becomes "0" when reading this register 12A1, and the BUSY bit on the other side becomes "0".

The SND bit indicates that a data transmission request has been accepted and the data transmission is possible. That is, when it is '1°, it indicates the transmission state. The RCV bit indicates that data is being received. That is, the receiving state is indicated when the angle is 11°.

The BUSY bit is set in the data register 11 when in the transmitting state.
When sending data is written to A, it becomes alm. R on the other side
When 1” is written to the 3TDT bit, this bit becomes ’0.
”.The DTRDY bit becomes “1” when transmission data is written to the data register 11B of the other party in the receiving state.
”.When “1” is written to the R3TDT bit, it becomes “0”.
becomes. Above control register 12A1.12A
The explanation for 2 is the control register 1 on the processor B side.
The same applies to 2B1.12B2.

FIG. 6 is a diagram showing the operation sequence of the present invention. The illustrated example shows a case where data is transferred from processor A to processor B. Control register 12A
, 12B is shown in FIG.

It is assumed that the system operates as shown in FIG.

Now, when processor A transfers data to processor B, processor A acquires the transmission right, so R
Turn on the QSND bit (set it to “1”; the same applies below)
After confirming that the SND bit is turned on, the transmission data read from the buffer memory 13A is written into the data register IIA.

On the other hand, on the processor B side, control register 12B
regularly leads. Then, when it detects that the RCv bit is turned on, it enters the reception state and DTRDY
When the bit is detected to be turned on, the data register I
The contents of the IB are read and the data is received, and then the data just received is immediately written into the data register 11B.

Then turn on the R8TDT bit. The contents of data register 11B are sent back to processor A.

After that, when processor A detects that the BUSY bit is turned off, processor A transfers the next transmission data to data register II.
Before writing to A, the contents of the data register 11A (return data from processor B) are read, and the buffer memory 13
A comparison is made with the original data stored in A. As a result of the comparison, if both data do not match, there is a data transmission error.

In this case, processor A turns on the FR3T bit and temporarily suspends transmission. Thereafter, error control is performed by turning on the RQSND bit again and retransmitting the data whose transmission failed. Thereafter, the next data is transmitted, and when the transmitted data and the returned data match, the next data transfer begins.

This data transfer sequence is repeated until the final data is sent.

Note that when data is retransmitted, according to rules decided in advance between processor A and processor 8, in the first retransmission, processor A inverts all bits of the data to be retransmitted as described above, and then writes the data to data register IIA. On the other hand, on the processor B side that has received the data, the received data is written in the data register IIB in the same form as return data. Thereafter, if the data on the processor A side is compared and both data match, all bits are inverted and used as received data. This received data is stored in the buffer memory 13B.

However, if both data still do not match, data transfer is performed in the manner described below. 7th
The figure is a diagram showing a specific data transfer sequence.

The example shown in the figure shows a case where the data transmission bits are 8 bits and the transmitted data is 028 (H indicates 16 ways. The same applies hereinafter).

In the figure, an X mark indicates a mismatch between both data (transfer data and return data on the processor A side), and a Q mark indicates a match between both data. In addition, the obstacles shown in the same figure are
This shows a defect in which the LSH bit line among the 8-bit data lines is fixed at "1 degree." It will be shown below that data can be transmitted normally even in such a case.

I have already mentioned up to the first retransmission. Since a mismatch occurred during the first retransmission, processor A retransmits the original data 02s.
is sent to processor B (second retransmission). The data received by processor B is 03o as in the first time. Processor B performs an ENOR with the first received data (that is, the second retransmitted data) and sets it to “1”.
Find the bit where it stands. The ENOR sequence can be expressed as data as follows.

First received data 0000 0011 Retransmission First received data 1111 1111 When the FOR (exclusive OR) of both of these data is taken, the following is obtained. Since ENOR is the negation of this, it becomes. '1
” is set in the lower two digits.

Since it was found that the lower two digit bits become "1" through such arithmetic processing, processor B removes 11 from the lower two digit bits for the received data for the second retransmission, and calculates the possible combinations. , 00°01.10, one bit at a time, and sends it back to processor A. Processor A repeats the transmission of the original data (first transmission data) from the second retransmission onwards until the original data and the returned data match.

In the example of FIG. 7, the original data and the returned data match on the fourth retransmission. This matched data is
This is the second transmission data (transfer data). If the data match, processor B stores the returned data in the buffer memory as transmission data.

In the above description, the case where processor A transfers data to processor B was explained as an example, but the present invention is not limited to this, and the same applies to the case where data is transferred from processor B to processor A. .

[Effects of the Invention] As described above in detail, according to the present invention, even if a fixed failure occurs between processors, data transfer between processors can be performed normally.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the principle of the method of the present invention, FIG. 2 is a block diagram of a computer system to which the present invention is applied, and FIG. 3 is a detailed configuration example of an embodiment of a computer system to which the present invention is applied. FIG. 4 is a diagram showing the meaning of each constituent bit when writing, FIG. 5 is a diagram showing the meaning of each constituent bit when reading, and FIG. 6 is a diagram showing the operation sequence of the present invention. FIG. 7 is a diagram showing a specific data transfer sequence, FIG. 8 is an explanatory diagram of a conventional repetitive transmission method, and FIG. 9 is a diagram showing the state of data transfer. In Figure 2, 11A and IIB are data registers, 12A and 12B are control registers, and 13A and 13
B is a buffer memory, and 14A and 14B are control programs.

Claims (1)

[Claims] In the case where processor A and processor B are connected via a data register and a control register, and data is transmitted between processor A and processor B using a control program, data is transmitted from processor A to processor B. The data is transferred (step 1), and processor B sends the received data back to processor A (step 2). Processor A reads the data returned from processor B while still in the sending state and compares it with the original data. (Step 3) If a mismatch occurs, processor A inverts all bits of the data and resends it to processor B (Step 4).
, Processor B returns the received retransmitted data as is to processor A (step 5), and processor A compares the returned data with the retransmitted data (step 6), and if a mismatch occurs, , processor A transfers the original data to processor B again (step 7), and processor B performs ENOR between the first received data and the first retransmitted data, and stores the bit that becomes 1. For the data that was found and retransmitted, the corresponding bit of the received data is changed to the bit pattern obtained by the combination of on/off of this bit and sent back (step 8), and in step 8, ENOR is taken and it becomes 1. A data transmission error control system characterized in that bit combination transmission is repeated on the processor A side until transmission data and return data match (step 9).