JPH02244336A - Data transmission error control system - Google Patents

Abstract

PURPOSE:To detect a data transmission error efficiently by sending data back in the order of reception from a reception-side processor, comparing the sent- back data with original data by a transmission-side processor, and sending the data back in reverse order from final data to dissident data by the reception-side processor if a dissidence is found. CONSTITUTION:The processor A transfers the data and the processor B stores the received data into a buffer memory 13B and sends the received data back to the processor A in the order of the reception. The processor A compares the sent-back data with the original data when a dissidence is found in the middle of the comparison, the processor A commands the processor B to quit sending the data back. Then the processor B reads the data out of the buffer memory 13B and sends the data back to the processor A in the reverse order from the final data to the dissident data this time. Further, the processor A compares the sent-back data with the original data to decide whether or not the data are transferred normally. Consequently, an error in the data transfer can be detected efficiently.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data transmission error control method when transmitting data between processors, more specifically, regarding a data transmission error control method when transmitting and receiving data using a repetitive transmission method. For the purpose of efficiently detecting data transfer errors between processors, a series of data transfers is performed from processor A to processor B. Processor B stores the received data in a buffer memory, and processor B stores the received data in a buffer memory. are returned to processor A in the order in which they were received, and processor A compares the returned data with the original data. If a mismatch occurs during the comparison, processor A transfers the data to processor B.
Processor B reads the data from the buffer memory and sends it back to Processor A in reverse order from the last received data to the mismatched data, and Processor A uses the returned data as the original. The configuration is such that it is compared with the data of

[Industrial Application Field] The present invention relates to a data transmission error control method when transmitting data between processors, and more particularly to a data transmission error control method when transmitting and receiving data using a repetitive transmission method.

When data is transmitted between processors, it is necessary to check whether the data has been transmitted correctly, and various data transmission error detection methods are used for this purpose. This data transmission error detection method needs to be accurate and reliable, but it must not take too much time to detect errors.

[Prior Art] When transmitting data between processors, there is a repeat transmission method as a method for checking whether data transmission has been performed accurately. FIG. 9 is an explanatory diagram of a conventional repetitive transmission system. Processor A has data holding register LA
, a data storage buffer memory 2A, and a control program (specifically, a CPU) 3A that controls these registers IA and buffer memory 2A, and processor B also has a similar register IB and buffer memory 2B.
and a control program 3B.

Now, assume that processor A transfers data stored in buffer memory 2A to processor B. The data stored in the buffer memory 2A is sequentially read out by the control program 3A, enters the register IA, and is transferred from the register IA to the processor B. 1st
FIG. 0 (a) is a diagram showing the state of data transfer. a, b, c from processor A to processor B
, d, . . . Processor B sequentially stores the received data in buffer memory 2b under the control of control program 3B. When processor A completes all data transfer, processor A notifies processor B to that effect.

Upon receiving the notification, processor B stores buffer memory 2.
Sequentially read the data stored in B and register IB.
The data are sent back to processor A in the order in which they are received. 10th
Figure (b) shows the order in which data is returned from processor B to processor A.
The order is d... Processor A compares the returned data with the original data stored in buffer memory 2A to check whether the data has been transmitted correctly. If all the data match, it is known that the data transmission from processor A to processor B was performed normally.

[Problems to be Solved by the Invention] In the conventional repetitive transmission method described above, there is no problem if all data transmission is successful, but if there is a discrepancy between the original data and the returned data on the processor A side. It becomes a problem if it occurs. In other words, if a mismatch occurs, all data is retransmitted from processor A to processor B from the beginning. In such a method, even though normal data transfer was being performed up to the time when a mismatch occurred, the data transfer has to be restarted from the beginning, which is wasteful. Furthermore, since the data transfer is restarted from the beginning, it takes a lot of time to transmit the data, and there is a problem that the transfer capacity is significantly reduced.

The present invention has been made in view of these problems, and an object of the present invention is to provide a data transmission error control method that can efficiently detect data transfer errors between processors.

[Means for Solving the Problems] FIG. 1 is a flowchart showing the principle of the system of the present invention. The present invention provides a method for transmitting a series of data from processor A to processor B when processor A and processor B are connected via a data register and a control register, and data is transmitted between processor A and processor 8 using a control program. Processor B stores the received data in the buffer memory (Step 1), Processor B sends the received data back to Processor A in the order it was received (Step 2), and Processor A stores the received data in its original form. In step 3), if a mismatch occurs during the comparison, processor A instructs processor B to stop sending back the data.Step 4), processor B reads the data from the buffer memory, and
Next, the data is sent back to processor A in reverse order from the last received data to the mismatched data.Step 5) Processor A compares the returned data with the original data to determine whether or not the data was transferred normally. (Step 6) It is characterized by being configured as follows.

[Operation] When a mismatch occurs on the processor A side, the processor B sends back the mismatched data to the processor A side in reverse order from the last received data to the mismatched data. If the data error is in the return from the processor B side, the final data to the mismatched data may become normal. In this case,
This confirms that all data was successfully transferred, so
Data retransmission becomes unnecessary. This is because it is known that the data was transferred normally from the first data to the mismatched data. If mismatched data occurs during data return, the data from the first mismatched data to the next mismatched data will be incorrect.

Therefore, since it is only necessary to transfer data from processor A to processor B during this period, there is no waste of data to be transferred. Therefore, according to the present invention, data transfer errors between processors can be detected efficiently.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of a computer system to which the present invention is applied. In the figure, processor A includes a data register 11A that holds data for transmission, and a control register 1 that holds data for mutually notifying each other of determining write mode or read mode, securing priority, etc.
2A, a buffer memory 13A in which transfer data is stored, and a control program 14A that controls data transmission. This configuration is the same on the processor B side, including a data register 11B, a control register 12B, a buffer memory 13B, and a control program 14.
It is composed of B. Control program 14A, 1
413 is specifically operated by a CPU (not shown).

In the system configured as described above, notification of priority reservation is sent from control registers 12A to 12B,
Assume that data is transferred from processor A to processor B. At this time, the data stored in the buffer memory 13A is transferred to the processor B side via the data register 11A under the control of the control program 14A.
On the processor B side, the data is stored in the buffer memory 13B under the control of the control program 14B. When a notification of completion of all data transfer is sent from control register 12A to 12B, processor B reads the data stored in buffer memory 13B and returns it to processor A sequentially from the first stored data via data register 11B. do.

On the processor A side, the returned data is successively compared with the original data stored in the buffer memory 13A. If all data match as a result of the comparison, the data transmission sequence ends. If mismatched data is generated as a result of the comparison, the control register 12A notifies the control register 12B of the mismatch. This time, the control program 14B reads the data stored in the buffer memory 13B starting from the last received data and returns the data to the processor A in reverse order up to the mismatched data.

On the processor A side, the data returned in reverse order is compared with the original data. If the data from the final data to the mismatched data match, it is known that all data has been transferred normally, and the data transmission sequence ends. Here, if a data mismatch occurs, the control register 12A notifies the control register 12B of the mismatch occurrence. Next, on the processor A side, the control program 14A resends only the data from the first mismatch point to the second mismatch point to the processor B.

FIG. 3 is a diagram showing retransmission data. In the figure, D1 is the mismatched data found in the first data return, and D2 is the mismatched data found in the next route data return. From start point S to Dl and from end point E to D
Since it is known that the data transfer up to Processor 2 was normal, the data area to be retransmitted from processor A to processor B is the area from D1 to D2 (the shaded area in the figure).

FIG. 4 is a diagram showing a detailed configuration example of an embodiment of a computer system to which the present invention is applied. The same thing as in Figure 2 is
Indicated with the same reference numerals. The figure shows the control registers 12A and 12B in detail. For example, regarding the processor A side, when sending control information from processor A to processor B (at the time of writing), the control register 12A1 is used;
When receiving control information from (at the time of reading), the control register 12A2 is used.

Control register 12A1 has RQSND bit, R
It consists of TSND bit, FR3T bit and RSTDT bit. This control register 12A
1 is used during writing, and the meaning of each constituent bit is as shown in FIG. The control register 12A2 is composed of an SND bit, an RCv bit, a BUSY bit, and a DTRDY bit. This control register 12A2 is used at the time of reading, and the meaning of each constituent bit is as shown in FIG.

When performing data transfer, the RQSND bit requests the transmission right by writing "1°."

When this transmission request is accepted, when this register 12A1 is read, the SND bit becomes "1" and the RCV bit on the other side becomes "1". The RTSND bit releases the transmission right by writing "1" when data transfer is completed.

When the transmission right is released, when 12 people read this register,
The SND bit becomes "0" and the RCV bit of the other party becomes "0".

The FR8T bit is written as "1" when data transmission is forcibly interrupted to perform error control.

With this operation, all bits of this register 12A1 are set to “
0", and the other party is in the same state. R8
The TDT bit is set to DTR when reading this register 12A1.
By writing "1" to this bit when the DY bit is "1", the DTRDY bit becomes "0" when reading this register 12A1, and the BUSY bit on the other side becomes "0".

The SND bit indicates that a data transmission request has been accepted and the data transmission is possible. That is, when it is "1", it indicates the transmission state. The RCV bit indicates that data is being received. That is, when it is "1", it indicates the receiving state.

The BUSY bit is set in the data register 11 when in the transmitting state.
When transmission data is written to A, it becomes "1". R on the other side
When “1” is written to the 3TDT bit, this bit becomes “
The DTRDY bit becomes '0'' when transmission data is written to the data register 11B of the other party in the receiving state.
1". Writing "11" to the R3TDT bit will set it to "0.
”.The above control registers 12A1, 12
The explanation of A2 is the same for the control registers 12B1 and 12B2 on the processor B side.

FIG. 7 is a diagram showing the operation sequence of the present invention. The illustrated example shows a case where data is transferred from processor A to processor B. Control register 12A
, 12B is shown in FIG.

It is assumed that the system operates as shown in FIG.

Now, when processor A transfers data to processor B, processor A acquires the transmission right, so R
Turn on the QSND bit (set it to “12”, the same applies below)
After confirming that the SND bit is turned on, the transmission data read from the buffer memory 13A is written to the data register 11.

On the other hand, on the processor B side, control register 12B
regularly leads. When it detects that the RCV bit is turned on, it enters the receiving state, and when it detects that the DTRDY bit is turned on, it reads the data register 11B and receives data, and then turns on the R3TDT bit.

After that, processor A has the BUSY bit turned off (“O”).
To become. (The same applies hereafter), the next transmission data is written into the data register 11A, and this operation sequence is repeated until the final data. When the transfer of all data is completed, the R8TSND bit is turned on to end the data transfer process. In the above description, the case where data is transferred from processor A to processor B has been explained as an example, but data transfer from processor B to processor A is completely the same.

FIG. 8 is a diagram showing a sequence example of the data retransmission method of the present invention. The data shown in ■ (N bytes) is processor A
It is assumed that processor B receives the data as shown in (3). The Xth byte of data is poorly received. In other words, the transmitted data is 141 ((H indicates hexadecimal), but the received data is 15H. This received data is returned from processor B as shown in ■, and processor A receives the X byte. There is an error (
mismatch).

As a result, processor A turns on the FRST bit and instructs processor B to stop sending back data. Processor B, which has detected this instruction, returns data in reverse order starting from the last received data FF□, as shown in ■. Processor A, which received this data, (N-(X-1)
) An abnormality is detected when the byte of data is received.

As a result, processor A turns on the FRST bit and issues an instruction to processor B to stop sending back. After that, the abnormal data (here, the X-th byte data 14I)
() is retransmitted to processor B as shown in ■.

This retransmitted data is received by processor B as shown in ■, and processor B retransmits the received data to processor A as shown in ■. Processor A, which has received this retransmitted data, compares it with the original data and recognizes that they match. This ends the transmission process.

In the above description, the case where processor A transfers data to processor B was explained as an example, but the present invention is not limited to this, and the same applies to the case where data is transferred from processor B to processor A. .

[Effects of the Invention] As explained in detail above, according to the present invention, the receiving processor first returns data in the order in which it was received, and the transmitting processor compares the returned data with the original data, so that a mismatch occurs. Then, by configuring the receiving processor to send back the data in reverse order from the last received data to the mismatched data, we have developed a data transmission error control method that can efficiently detect data transfer errors between processors. can be provided, which has great practical effects.

[Brief explanation of drawings]

Fig. 1 is a flowchart showing the principle of the method of the present invention, Fig. 2 is a block diagram of a computer system to which the invention is applied, Fig. 3 is a diagram showing retransmitted data, and Fig. 4 is a computer system to which the invention is applied. A block diagram showing a detailed configuration example of an embodiment of the system, FIG. 5 is a diagram showing the meaning of each constituent bit at the time of writing, FIG. 6 is a diagram showing the meaning of each constituent bit at the time of reading, and FIG. 7 is a diagram showing the meaning of each constituent bit at the time of reading. FIG. 8 is a diagram showing an example of the sequence of the data retransmission method of the present invention. FIG. 9 is an explanatory diagram of the conventional repetitive transmission method. FIG. 10 is a diagram showing the state of data transfer. It is. In Figure 2, 11A and IIB are data registers, 12A and 12B are control registers, and 13A and 13
B is a buffer memory, and 14A and 14B are control programs.

Claims (1)

[Claims] When processor A and processor B are connected via a data register and a control register, and data transmission between processor A and processor B is performed by a control program, a series of data transmission from processor A to processor B is provided. Processor B stores the received data in the buffer memory (Step 1), Processor B sends the received data back to Processor A in the order in which it was received (Step 2), and Processor A stores the received data in the buffer memory (Step 2). The data is compared with the original data (step 3), and if a mismatch occurs during the comparison, processor A instructs processor B to stop sending the data back (step 4), and processor B transfers the data from the buffer memory. read the data,
This time, the data is sent back to processor A in reverse order from the last received data to the mismatched data (step 5), and processor A compares the returned data with the original data to determine whether or not the data was transferred normally. A data transmission error control system characterized in that it is configured to (step 6).