JPS60254242A - Buffer control system - Google Patents

Abstract

PURPOSE:To apply easily a retrial function to the transfer of data by performing a data parity check when the transferred data is received and delivering a request for retransfer of data in case a parity error is detected. CONSTITUTION:A buffer device writes an error display ''1'' on the corresponding position of a buffer 10 when a parity error is detected with the received data. At the same time, the present contents of a write address register 12 on an address register 19 and preserved there. While the signals are transmitted via a control line 20 of a common bus 5 to give a request for retransmission of data to a device that actually transferred data. A gate 22 is controlled as soon as the retransmitted data is received by the bus 5. Therefore, the contents of an address holding register 19 are used as a write address to write both the received data and the parity check result to the buffer 10 like the ordinary reception. Here the transmission of data is performed again in case a parity error is detected again.

Description

Detailed Description of the Invention (a) Industrial Field of Application The present invention relates to the control of data exchange between devices in a computer system, etc., and in particular, the control of the reception buffer when a parity error occurs in data transfer between devices. Regarding control method.

In data transfer between devices such as computer systems,
It is widely used to detect errors during transfer by so-called parity checking.

Errors that occur during transfer are often caused by temporary external noise, etc. In such cases, recovery often occurs naturally, so errors caused by fixed failures in the transfer path itself are not considered. It is desirable to continue the functioning of the system by taking measures different from the case.

(b) Prior Art For this reason, conventional systems use a method of retrying the transfer when a parity error in transfer data is detected.

(Problem to be solved by the C1 invention) However, if there is an error even after retrying, it is necessary to retry the process a reasonable number of times without interfering with the operation of the system and to the extent that it is effective to remedy the error due to temporary causes. It is necessary to abort the trial and switch control to failure processing, etc. Because such additional control functions are required, the retry function as described above is used only in relatively large and expensive devices.

An object of the present invention is to provide a simple control method for introducing a retry function into data transfer between devices.

Means for solving the fd1 problem This purpose is to perform a parity check on the data when the common control device receives the data transferred from a plurality of devices and has the function of sequentially receiving the data and holding it in a buffer. If a parity error is detected, a predetermined error indication is set in the buffer, a retransmission request is issued for the data, the data is received, and the error is cleared as normal data is received. This is achieved by the buffer control method of the present invention, which is configured to erase the display.

(e) Effect: When the receiving device detects a parity error in the received data, it displays an error in the buffer location where the data should be stored, retries the data transfer, and is unable to receive the data normally. The erroneous display shall be deleted only if the error occurs. Therefore, if normal reception is not possible even after repeated retries, at the point when the received data needs to be processed,
If there is an error indication when reading the buffer, it is sufficient to proceed to appropriate fault handling.

(f) Embodiment FIG. 2 is a system configuration diagram in an embodiment of the present invention. In the figure, reference numeral 1 denotes a plurality of devices on the data sending side, such as line adapters of a communication control device, which are connected to the buffer control device 2 via a common bus 5.

The buffer control device 2 controls the common bus in a known manner,
It accepts a transfer request from device 1, receives data transferred from device 1, and holds it in a buffer within the device.

The processing device 3 sequentially retrieves and processes the data held in the buffer from a large number of devices 1, and transfers the received data to the storage device 4, so that the buffer can be used for the next received data. do.

FIG. 1 is a block diagram showing details of the buffer control device 2 of FIG. 2. As shown in FIG.

The data received from the common bus 5 is sequentially stored and held in Wllo-1 of the word at each address of the buffer 1°, and a parity check is performed by the parity check circuit 11, and the check result (for example, if normal reception is 0゛, error indication °1') is written in the word column 10-2 corresponding to the data in the buffer.

The write address of the received data to the buffer 10 is specified by the write address register 12, and is updated to the next word address by the increment circuit 13 when the above writing related to reception is completed.

The processing device 3 in FIG. 2 reads and processes the word at the address indicated by the read address register 14 in FIG. 1, and then the read address is updated by the increment circuit 15 to the next word address.

The contents of the successive address register I4 and the write address register 12 are compared by the comparator circuit 16, and the signal line 1 is
7 to the processing device 3, and the processing device 3 sequentially processes the contents of the sofa 1o until both addresses match.

When the buffer control device 2 detects a parity error in the received data, it writes the error indication 1゛ to the corresponding position of the buffer 10 as described above, and also writes the error indication 1゛ by the signal 18.
Write address register 1 to address holding register 19
Set and save the current contents of 2.

Furthermore, by sending a signal through the control line 2o of the common bus 5, the device 1 that has actually transferred the data is requested to retransmit the data.

When retransmission data is received via the common bus 5, the gate 22 is controlled by a signal sent from the corresponding device 1 to the control line 21 at the same time, so that the address holding register 1
Using the contents of 9 as a write address, the received data and the parity check result are written to the buffer 10 in the same way as normal reception.

If there is a parity error again, retransmission is performed in the same manner as described above, except that the contents of the address holding register 19 are saved as they are.

As described above, when normal data is received by retransmission, the error display in the column 10-2 of the buffer 10 is updated to a normal result of 0°.

The processing device 3 sequentially processes the received data in the buffer 10 as described above, but if normal data can be received by the above retransmission operation before processing the word address of the received data in which an error has occurred. Normal processing is performed without being concerned about the occurrence of an error.

If normal data cannot be received even after repeated retransmissions, and the processing device 3 attempts to process the word address of the received data in which an error has occurred, the processing device 3 reads data from the column 10-2 of the buffer 10. Since it detects incorrect display,
As in the past, fault processing is started and common bus tests are performed.

(g1 Effect of the Invention As is clear from the above explanation, according to the present invention, it is possible to introduce a data transfer retry function by adding a relatively simple means, thereby improving the reliability and economic efficiency of computer systems, etc.) This has a significant industrial effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a buffer control device according to an embodiment of the present invention, and FIG. 2 is a system configuration diagram according to an embodiment of the present invention. In the figure, 2 is a buffer control device, 3 is a processing device, 10 is a buffer, 10-2 is an error display column, 11 is a parity check circuit, 12 is a write address register, 14 is a read address register, 19 is an address holding register, 20 indicates a retransmission request control line.

Claims (1)

[Claims] Upon reception of the above transfer data by the common control device, which has the function of sequentially receiving data transferred from multiple devices and holding it in a buffer, a parity check is performed on the data, and if a parity error is detected, the above It is configured to set a predetermined error indication in the buffer, issue a retransfer request for the data, re-receive the data, and erase the error indication when normal data is received. Characteristic buffer control method.