TWI261993B - System and method for data redundancy checking and correcting - Google Patents

Abstract

A system and method for data redundancy checking and correcting are applied to a peripheral controller, the method comprising the steps of determining whether a data block coming from the peripheral device contains error(s); storing indicator(s) that indicates the data bit(s) containing the error(s); identifying the error bit(s) indicated by the indicator(s); and correcting the error(s) in the error bit(s). Instead of storing the whole data block, only the indicator(s) indicating the error(s) is/are stored, thereby a buffer for accommodating the entire data block and the cost of such are eliminated.

Description

1261993 V. INSTRUCTIONS (1) [Technical Field of the Invention] The present invention generally relates to a data error checking and correction processing system and method, and more particularly to a data applied to a controller for connecting peripheral devices System and method for error checking and correction. [Prior Art] One of the main problems of all transmission systems is how to deliver the originally delivered information to the destination. In response to this demand, many different algorithms have been developed today, such as peer checking (p a r i t y c h e c k ), or Cyclic Redundancy Check (CRC), etc. to check received data. The CRC performs a round-robin algorithm for one (multiple-bit) data to generate redundant information about the content and organization of the data and uniquely identifies the block. Therefore, the CRC can be used to check the correctness of the transmitted data. These data check codes are usually sent to the receiving end together with the actual required data. The data stream containing the actual data and the data check code is hereinafter referred to as the "data block". The receiving end generates a redundant data for performing the calculation on the received data, and compares the generated redundant data with the redundant data in the received data block; if the two redundant data are the same, it represents the received data. Correct, otherwise, the data contains errors, and the receiving end can ask the sender to retransmit the data block. However, both the parity check and the CRC can only know whether the data is correct or not, and cannot know the location of the wrong bit in the data, so the error correction cannot be performed. Therefore, another error checking and correction (Error Checking a n C C r r r e c t i ο n C o d e ; E C C ) code has been proposed for checking the integrity of the data, and finding and correcting the erroneous bits in the data. According to different kinds of error check

17591 Jin Li.ptd Page 7 1261993 V. Invention Description (2) The correction code can correct one or more error bits. Similarly, the process of error checking and correction is that the receiving end generates a corresponding error check and correction code for the data in the data block, and performs an operation on the received error check and correction code to know whether the data is correct. . If it is not correct, correct the bit that needs to be corrected. For the correction of the binary bit, it is corrected by changing 1 to 0 or 0 to 1. The error check and correction code can be applied to the flash controller (f 1 ashc ο ntr ο 1 1 er ) in the microprocessor unit, connected to the external flash memory device, and responsible for the data from the flash memory device. The system bus is transferred to the microprocessor. Before the controller transmits the data to the system bus, it uses the error check and calibration code to check whether the received data is correct and correct the error data. When the conventional flash controller processes the error check and correction operation of the data, the data needs to be read and stored in the buffer (bu ff er ) of the flash controller, and at the same time, the data is checked for errors and corrected. After the data bit containing the error is found, the bits containing the erroneous data stored in the buffer are corrected, and then the corrected data is transmitted to the system. However, the buffer in this prior art must have enough space to store the entire data block, which will result in an increase in space and hardware costs. Therefore, the present invention proposes a method and system for data error checking and correction, which can complete error checking and correction of data without storing the entire data block, thereby saving the cost and the occupied hardware space of the buffer. SUMMARY OF THE INVENTION The main object of the present invention is to provide a data error check and correction

1759] Jin Li.ptd Page 8 1261993 V. Invention Description (3) Processing system and method, by storing only the indicator indicating the error bit instead of the entire data block, thus eliminating the cost and space of the buffer . The present invention provides a controller in a processing system for controlling data between an external device connected to the processing system and an internal bus bar of the processing system, the controller including reading for reading data from an external device Module; error checking and correction processing system for performing error checking and correcting operations to determine whether the data read by the reading module is incorrect, and recording only the indicator indicating the bit containing the error instead of storing the entire data block When the data is read sequentially by the reading module, it is judged whether the current data bit read from the external device is an error, and if so, the data of the bit is corrected; and the transmitting module is used to cause an error. The data that is checked and corrected by the calibration processing system is sent to the processing system bus. The invention provides a system for data error checking and correction, which can be applied to the above controller for checking and correcting any error data. The system for checking and correcting the data includes: an error checking and correcting operation module, Performing an error check and correction operation on the data block transmitted from the external device, and determining a bit containing the error according to the operation result; a memory for storing the indicator indicating the bit containing the error; and an error data identification The module is configured to identify whether the currently read data bit is incorrect according to the indicator in the storage; and a correction module for correcting the data in the error bit. The present invention provides a method for data error checking and correction, comprising the following steps: First, an error checking and correcting operation module performs error checking and correcting operations on the read data block to determine whether the data block includes

17591 金丽.ptd Page 9 1261993 V. Invention Description (4) There is an error; secondly, the error checking and correction calculation module finds the bit containing the error data, and records the indicator indicating the error bit in In a memory; then, an error data discrimination module determines whether the currently read data bit is erroneous according to the indicator recorded by the memory; finally, a correction module corrects the wrong bit. [Embodiment] Fig. 1 is a block diagram showing components and an external flash memory device in a microprocessor system relating to the present invention. As shown, the microprocessor 1 system includes a flash controller 10 and a system bus 20. The flash controller 10 is used to control the transfer of data between the microprocessor 1 and the external flash memory device 2. The flash controller 10 includes at least a read module 1 0 1 , an error check and correction processing system 1 0 2, and a transmission module 1 0 3 . The reading module 101 is responsible for reading the data block from the external flash memory device 2. For example, the data block can be composed of the actual data of 64 bits and the 7-bit error checking and correction code corresponding to the data. . Error check and correction processing system 1 0 2 pin The error check and correction operation are performed on the data block read by the read module 1 0 1 , including determining the error bit and correcting it. The transmitting module 1 0 3 transmits (corrected) uncorrected data to the system bus 20 . Figure 2 illustrates an error checking and correction system 102 coupled to flash controller 10 in accordance with an embodiment of the present invention. The error checking and correction system 1 0 2 includes an error checking and correcting operation module 2 1 0, a register 2 2 0, a bit comparison module 2 3 0, and a correction module 2 4 0. Error checking and correction computing module 2 1 0 operation reading module 1 0 1 read the data block to generate a corresponding error check and correction code, and receive

Ml ___ 17591 Jin Li.ptd Page 10 1261993 V. Invention Description (5) The error check and the correction code are calculated, and the data is judged according to the result of the operation, and the position of the error bit is judged. If the data is correct, it is transmitted to the system bus 20 by the transmitting module 103. The register 2 2 0 is used to store an indicator indicating the bit of the error data, such as the address of the bit. According to an embodiment, the addresses of the error bits can be recorded in a tabular manner, and reference is made to FIG. 3, which illustrates an example data block 300 containing errors and a register in accordance with an embodiment of the present invention. 2 2 0 error table 2 2 1. In this embodiment, the data block 300 is composed of a 64-bit actual data 3 0 1 and a 7-bit error check and correction (ECC) code. The actual data 3 0 1 contains 2 error bits, which are bit 3 and bit 15 respectively. As described above, when the error check and correction operation module 2 1 0 determines the address of the error bit according to the operation result, that is, the bit address in the data block 300 (hereinafter referred to as a bit address) 3 and 1 5, the address points containing the errors are stored in the error table 2 2 1 as shown. Therefore, the error bit address stored in error table 2 2 1 is in the order of small to large, followed by 3 and 15 . The indicator used to indicate the error bit in the present invention is not limited to the address of the bit. Of course, any other way may be used to indicate the bit in the data block that contains the error, for example, using the relative bias of each element from a specific reference point. Transfer and so on. It should be noted that embodiments of the present invention store only the indicator indicating the error bit, meaning the bit address, rather than storing the entire data block. Therefore, the cost and space occupied by the buffer can be effectively saved. The data bit in the flash memory device 2 is read sequentially by the reading module 1 0 1 , and the address comparison module 2 3 0 determines the address of one of the data bits currently read and the register 2 2 0 error table 2 2 1 error bit address is met,

17591 Jin Li.ptd Page 11 1261993 V. Invention Description (6) If the two-digit address matches, it means that the data bit currently read contains errors. The correction module 2404 then corrects the address comparison module 2300 to identify the data bit containing the error. Next, a method of processing error checking and correction according to an embodiment of the present invention will be described with reference to FIG. The method includes the following steps: First, step 4 0 is performed, and the error checking and correction computing module 2 1 0 performs operations on the data sequentially read by the reading module 1 0 1 to generate an error check and a correction code. And it performs error checking and correction calculation with the original error check and correction code 3 0 2 in the data block 300 to determine whether the data block is correct. If there is no error in the entire data block, proceed to step 4 0 9; if no, proceed to step 4 0 2 . It should be noted that in this step 410, only the data block 300 is read sequentially to perform error checking and correction operations without storing the entire data block in the error checking and correction processing system. Therefore, it is not necessary to provide the space for storing the entire data block and the cost of implementing the buffer as is conventional. In step 4 0 2, the error checking and correction computing module 2 1 0 finds that the error data is located in the address in the data block 300, that is, the bit addresses 3 and 5, and records the error bit addresses. In the error table 2 2 1 of the register 2 2 0, as in the manner of the above FIG. Go to step 4 0 3. In step 403, the data bit of the flash memory device 2 is read again in sequence, so that the address comparison module 2300 will read the currently read data bit address and the current bit in the error table. The meta-locations are compared to determine whether the two-dimensional addresses are the same. If they are the same, it means that the bit address currently read contains an error, and step 4 0 4 is performed; if not, step 4 0 6 is performed. In section 3 of the data block 300

17591 金丽.ptd Page 12 1261993 V. Invention Description (7) In the embodiment, the address comparison module 203 will start from the first read bit until the third bit is read. When the error bit address 3 stored in the error table 2 2 1 is the same as the bit address 3 currently read, therefore, step 4 0 4 ° is performed in step 4 0 4 to make the correction module 2 4 0 The data bit is corrected and sent to the transmitting module 1 0 3 for transmission to the system bus 20 . Then proceed to step 4 0 5 . In step 405, the correction module 2404 determines whether the current error bit address of the error table is the last error bit address. If yes, the process of error checking and correction is ended. Otherwise, proceed to step 4 0 8. In this embodiment, if the correction module 240 corrects the error data of the bit address 3, it proceeds to step 4 0, and if the error data is corrected to the bit address 15, the error bit is The address 1 5 is the error bit address of the last record in the error table 2 2 1 , indicating that all the data bits containing the error have been corrected, and therefore, the error checking and correction process is ended. In step 406, the correction module 240 sends the error-free bit to the transmitting module 1 0 3, and then proceeds to step 407. In step 407, the read module 1 0 1 reads the next bit of the data block, and then returns to step 4 0 3 . In step 4 0 8, the error bit address is entered in the error table, and then returns to step 4 0 7 . In step 409, the read module 1 0 1 reads and sends all the data bits of the data block to the sending module 1 0 3 in sequence, and after completion, ends the processing error checking and correction process. .

1759] Jinli.ptd Page 13 1261993 V. INSTRUCTIONS (8) The above examples are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and alterations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later.

17591 金丽.ptd Page 14 1261993 Brief description of the drawing [Simple description of the drawing] Fig. 1 is a block diagram showing the components of the microprocessor system and the external flash memory in the microprocessor system; An error check and correction system according to an embodiment of the present invention in a flash controller; FIG. 3 illustrates a data block containing an error and a corresponding error table stored in the register according to an embodiment of the present invention; A flow of error checking and correction processing according to an embodiment of the present invention. (Component Symbol Description) 1 Microprocessor 2 Flash Memory Device 10 Flash Controller 20 System Bus 101 Read Module 102 Error Check and Correction (ECC) Processing System 103 Transmit Module 210 Error Check and Correction (ECC) Operation Module 220 Register 221 Error Table 230 Address Control Module 240 Correction Module 300 Data Block 301 Data 302 Error Correction (ECC) Code

17591 Jin Li.ptd第15页

Claims (1)

1261993 VI. Patent Application Range 1. A method for data error checking and correction processing, which can be applied to a controller of a processing system for controlling an external device connected to the processing system and a processing system convergence The data communication between the rows, the data error checking and correction method comprises the following steps: (1) causing an error checking and correction computing module to perform error checking and correction (ECC) on the data block read from the external device, To determine whether the data block contains an error; (2) causing the error checking and correction computing module to find a bit containing the erroneous data and record the indicator indicating the erroneous data bit in a storage; (3) Having an error data identification module identify a data bit containing the error for the current data bit read from the external device based on the indicator stored in the memory; and (4) causing a correction module to correct the error Data bit. 2. The method of claim 1, wherein the error data identifying module identifies the data bit containing the error for the current data bit read from the external device, including comparing the current data bit Whether it is the bit indicated by the indicator recorded in the memory, and if so, the bit indicated by the indicator contains an error. 3. If the method of claim 1 or 2 is applied, the indicator may include the address of the error bit. 4. The method of claim 3, wherein the step of identifying the data bit containing the error for the current data bit read from the external device by the error data discrimination module comprises sequentially comparing the current data bit 17591 金丽.ptd Page 16 1261993 6. Whether the address of the patent scope element meets the address of the error bit recorded in the memory. If the two sites match, it means that the bit currently read contains error. 5. A controller located in a processing system for controlling communication of data between an external device connected to the processing system and a processing system bus, the controller comprising: a reading module, reading in sequence Taking data from an external device; an error checking and correction processing system, determining whether the data read by the reading module is incorrect, and recording only the indicator indicating the bit containing the error instead of storing the entire data block, When the reading module reads the data sequentially, it judges whether the data of the current bit read from the external device is incorrect according to the stored index, corrects the data of the bit if there is an error, and a transmitting module. It is used to send the data processed by the error checking and correction processing system to the processing system bus. 6. The controller of claim 5, wherein the error checking and correction processing system determines whether the data read by the reading module is misidentified, including indicating whether the current data bit is an indicator of the record. The bit, if it is, represents the bit indicated by the indicator contains an error. 7. The controller of claim 5 or 6, wherein the indicator may include the address of the error bit. 8. The controller of claim 7, wherein the error checking and correction processing system determines whether the data read by the reading module is incorrect, including whether the address of the current data bit matches the record sequentially. For storage 1759] Jin Li.ptd Page 17 1261993 VI. The address in the patent application scope, if the two addresses match, it means that the bit currently read contains an error. 9. The controller of claim 8 wherein the reservoir is a register. A system for data error checking and correction processing, which can be applied to a controller of a processing system for controlling data between an external device connected to the processing system and a processing system bus The communication, the data error checking and correction system includes: an error checking and correcting operation module for judging whether the data read from the external device is incorrect; a memory for storing the error checking and correcting operation The module determines that the indicator containing the wrong bit is not stored, instead of storing the entire data block; an error data identification module is configured to determine whether the currently read data is an incorrect data bit according to the indicator in the storage. And a correction module for correcting the data bit when the error data identification module determines that the data of the currently read bit is an error. 1 1 · The system of claim 10, wherein the error data identification module determines whether the currently read data bit is a bit indicated by an indicator recorded in the storage, and if so, the representative The indicator indicated by this indicator contains an error. 1 2 • A system as claimed in claim 10 or item 11, wherein the indicator stored in the memory may include the address of the error bit. 17591 金丽.ptd Page 18 1261993 VI. Application for Patent Range 1 3. For the system of claim 12, wherein the error data identification module includes an address comparison module for sequential comparison Whether the address of the current data bit matches the address recorded in the memory. If the two addresses match, it means that the bit currently read contains an error. 1 4. The system of claim 1, wherein the storage device is a temporary storage device. 17591 Jin Li.ptd第19页