JPS5812955U - Resin-encapsulated semiconductor device - Google Patents

Resin-encapsulated semiconductor device

Info

Publication number
JPS5812955U
JPS5812955U JP1981107913U JP10791381U JPS5812955U JP S5812955 U JPS5812955 U JP S5812955U JP 1981107913 U JP1981107913 U JP 1981107913U JP 10791381 U JP10791381 U JP 10791381U JP S5812955 U JPS5812955 U JP S5812955U
Authority
JP
Japan
Prior art keywords
substrate
resin
semiconductor device
spacer
encapsulated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981107913U
Other languages
Japanese (ja)
Other versions
JPS6144438Y2 (en
Inventor
桜井　康仁
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1981107913U priority Critical patent/JPS5812955U/en
Publication of JPS5812955U publication Critical patent/JPS5812955U/en
Application granted granted Critical
Publication of JPS6144438Y2 publication Critical patent/JPS6144438Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は封止をより完全にするため考案され
た半導体装置の断面図、第３図は本考案半導体装置の分
解斜視図、第４図は本考案半導体装置の組立斜視図、第
５図は第４図のＡ−Ａ’断面図である。 １、　６．　９・・・絶縁性基板、２．　８．　１４・
・・半導体素子、３．　７．　１０・・・対向基板、４
．１１・・・スペーサ、１２・・・放熱部。1 and 2 are cross-sectional views of a semiconductor device devised for more complete sealing, FIG. 3 is an exploded perspective view of the semiconductor device of the present invention, and FIG. 4 is an assembled perspective view of the semiconductor device of the present invention. , FIG. 5 is a sectional view taken along the line AA' in FIG. 4. 1, 6. 9... Insulating substrate, 2. 8. 14・
...Semiconductor element, 3. 7. 10... Opposite board, 4
．． 11... Spacer, 12... Heat dissipation part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板と該基板表面に貼着された半導体素子と、この基板
表面に設けられたスペーサと、このスペーサを介して前
記基板と対向して上記半導体素子を挾み込むように設け
た対向基板と、前記両基板間に充填された樹脂と、から
成り、上記スペーサは熱伝導慶大なる材料に依って構成
されると共にその一部を前記両基板間から外方へ突出さ
せた事を特徴とする樹脂封止半導体装置。A substrate, a semiconductor element attached to the surface of the substrate, a spacer provided on the surface of the substrate, and a counter substrate provided opposite to the substrate with the semiconductor element sandwiched therebetween, with the spacer interposed therebetween. a resin filled between the two substrates, and the spacer is made of a thermally conductive material, and a portion of the spacer protrudes outward from between the two substrates. Resin-sealed semiconductor device.
JP1981107913U 1981-07-20 1981-07-20 Resin-encapsulated semiconductor device Granted JPS5812955U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981107913U JPS5812955U (en) 1981-07-20 1981-07-20 Resin-encapsulated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981107913U JPS5812955U (en) 1981-07-20 1981-07-20 Resin-encapsulated semiconductor device

Publications (2)

Publication Number Publication Date
JPS5812955U true JPS5812955U (en) 1983-01-27
JPS6144438Y2 JPS6144438Y2 (en) 1986-12-15

Family

ID=29902338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981107913U Granted JPS5812955U (en) 1981-07-20 1981-07-20 Resin-encapsulated semiconductor device

Country Status (1)

Country Link
JP (1) JPS5812955U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171663A (en) * 2010-02-22 2011-09-01 Mitsubishi Electric Corp Resin-sealed electronic control device, and method of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171663A (en) * 2010-02-22 2011-09-01 Mitsubishi Electric Corp Resin-sealed electronic control device, and method of fabricating the same
US8274791B2 (en) 2010-02-22 2012-09-25 Mitsubishi Electric Corporation Resin-sealed electronic control device and method of fabricating the same

Also Published As

Publication number Publication date
JPS6144438Y2 (en) 1986-12-15

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