JPS58125839A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58125839A
JPS58125839A JP57008162A JP816282A JPS58125839A JP S58125839 A JPS58125839 A JP S58125839A JP 57008162 A JP57008162 A JP 57008162A JP 816282 A JP816282 A JP 816282A JP S58125839 A JPS58125839 A JP S58125839A
Authority
JP
Japan
Prior art keywords
pads
beams
semiconductor device
pad
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57008162A
Other languages
Japanese (ja)
Inventor
Minoru Kanbara
実 神原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57008162A priority Critical patent/JPS58125839A/en
Publication of JPS58125839A publication Critical patent/JPS58125839A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the defective recognition of the position of a metallic pad by coating the whole surface of a chip except a junction region with coloring resin capable of discriminating beams. CONSTITUTION:A coloring agent having no adverse effect on a semiconductor element is mixed with polyimide resin, and reflectivity or transmittance is lowered from a predetermined value to prescribed wavelength beams. The whole surface of the chip except the pads 4 is coated with the resin film 7. According to the constitution, the rate of defective recognition of the pads is reduced remarkably because wetproof property is improved by the film 7, an electrode is protected and contrast among the pads 4 and other sections is increased at scanning by beams.

Description

【発明の詳細な説明】 本発明は半導体装置、特に自動ボンディング装置を使用
するのに好適な半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure of a semiconductor device suitable for use in an automatic bonding device.

半導体装置製造の自動化が進行する中で、リード線のボ
ンディング工程も手動方式から自動化へと進められてい
る。ボンディング工程の自動化にかいて最も重要な点は
、チップ面上の所定の金属電極パッド上にリード線が確
実にボンディングされるように該金属電極パッドの存在
位置を自動ボンダーに自動認識させるためのパターン認
識機構である。As the automation of semiconductor device manufacturing progresses, the lead wire bonding process is also progressing from manual methods to automation. The most important point in automating the bonding process is to have the automatic bonder automatically recognize the location of the metal electrode pad on the chip surface so that the lead wire is reliably bonded onto the metal electrode pad. It is a pattern recognition mechanism.

金属電極パッドの認識方式としては、光を照射しながら
チップ面上を走査し、その反射光を信号として検出して
、この検出信号の中から前記金属電極パッドに相当する
信号を読み取るものが通常である。この方式によると、
チップ面上の金属電極パッドではなく、金属電極パッド
と同形もしくは類似形あるいは同サイズや類似サイズの
金属部Ｋ例えば配線層や拡散等で使用される位置検出マ
ーク等）を前記金属電極パッドと誤認識してしまい、誤
ったボンディングを行なうという欠点ヂがあった。The usual method for recognizing metal electrode pads is to scan the chip surface while irradiating light, detect the reflected light as a signal, and read the signal corresponding to the metal electrode pad from among the detected signals. It is. According to this method,
Rather than a metal electrode pad on the chip surface, a metal part (such as a position detection mark used in a wiring layer or diffusion, etc.) that is the same shape, similar shape, or size as a metal electrode pad is mistaken for the metal electrode pad. There was a drawback that the bonding could be performed incorrectly due to the recognition.

本発明の目的は、誤認識を防止した半導体装置の構造を
提供することである。An object of the present invention is to provide a structure of a semiconductor device that prevents misrecognition.

本発明の半導体装置はボンディング領域以外のチップ表
面全面を光識別可能な着色樹脂で覆ったことを特徴とす
る。The semiconductor device of the present invention is characterized in that the entire surface of the chip other than the bonding area is covered with a colored resin that can be optically identified.

次に図面を用いて本発明の一実施例を詳述する。Next, one embodiment of the present invention will be described in detail using the drawings.

一般に半導体装置のチップ面上には第１図（ａ）に示す
ように、半導体基板ｌ内の素子領域２から引き出された
配線３の端部にポンディングパッド部４を有している。Generally, on the chip surface of a semiconductor device, as shown in FIG. 1(a), a bonding pad portion 4 is provided at the end of a wiring 3 drawn out from an element region 2 in a semiconductor substrate 1.

しかし、このポンディングパッドが設けられる位置の周
辺には別の金属部５を有する。尚、６は酸化膜であり、
第１図ｔｂ）はポンディングパッドを別の位置からとら
え九断面図であるＯ 従来では前記チップ面上に耐湿性の向上の丸めや、金属
電極保護のために通常のポリイ建ド（ｌＩｔ脂を被覆し
ていた。このポリインドはポンディングパッド４の自動
認識の際に用いられるセンサー、たとえばＣＯＤや撮儂
管が検出できる光の波長範囲においてｔｌぼ透明である
ので、走査中にポンディングパッド２とほぼ同じ形状あ
るいはほぼ同じ面積を有する他の金属ＷＡ５をポンディ
ングパッド２としてｇ＠してしまう確率が非常に高い。However, there is another metal part 5 around the position where this bonding pad is provided. In addition, 6 is an oxide film,
Figure 1 (tb) is a cross-sectional view of the bonding pad taken from a different position.In the past, ordinary polyimide resin was used to round the chip surface to improve moisture resistance and to protect the metal electrodes. This poly ind is completely transparent in the wavelength range of light that can be detected by sensors used for automatic recognition of the bonding pad 4, such as COD and camera tubes. There is a very high probability that another metal WA5 having approximately the same shape or approximately the same area as the bonding pad 2 will be used as the bonding pad 2.

本実施例では、従来のポリイばド膜４に変えて、あるい
はその上（すなわち下層透明ポリイずドの上）Ｋヂッグ
全面にわたって、ポリイミド樹脂中に半導体素子の特性
や信頼性に影響を与えないような着色剤を混合して、少
なくとも所定の波長をもつ光に対して反射率あるいは透
過率のうち少なくともどちらか一方が所定の値よりも小
さくなるようＫした被覆膜７（例えば着色ポリイミド樹
脂）を設けている。即ち、第１図（ｃ）に平面図を示す
ようにこの被覆ｌ［７によってポンディングパッド４以
外のチップ表面は完全に覆われている。In this embodiment, instead of the conventional polyimide film 4 or on top of it (i.e., on the lower transparent polyimide film), a polyimide film 4 is applied over the entire surface of the K-zig, which does not affect the characteristics or reliability of the semiconductor element. A coating film 7 (for example, a colored polyimide resin) is prepared by mixing coloring agents such as ) has been established. That is, as shown in the plan view of FIG. 1(c), the chip surface other than the bonding pad 4 is completely covered by this coating l[7.

前記構造を適用すれば被覆！Ｑ［７によって耐湿性中金
属電極保護も更に保障され、かつ光走査８においてポン
ディングパッドとそれ以外の部分のコントラストが大き
くとれるのでパッドのｗ４ｉｉ繊率が著しく低下し、作
業性も向上する。If you apply the above structure, it will be covered! Q[7 further ensures protection of metal electrodes during moisture resistance, and the contrast between the bonding pad and other parts can be increased in optical scanning 8, so the w4ii fiber rate of the pad is significantly reduced and workability is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ｆｍ）　、　ｆｂｌ　、　＋ｃ）は夫々本発明の
一実施例による半導体装置の角度の異なる構造断面図と
平面図である。 ｌ・・・・・・半導体基板、２・・・・・・素子領域、
３・・・・・・配線、４・・・・・・ポンディングパッ
ド、５・・・・・・配線、６・・・・・・酸化膜、７・
・・・・・被覆膜、８・・・・・・光走査。 第　ｌ　薗FIGS. 1 fm), fbl, and +c) are a structural sectional view and a plan view at different angles of a semiconductor device according to an embodiment of the present invention, respectively. l... Semiconductor substrate, 2... Element region,
3...Wiring, 4...Ponding pad, 5...Wiring, 6...Oxide film, 7...
...Coating film, 8...Light scanning. Part I

Claims (1)

【特許請求の範囲】[Claims] ポンディングパッドを有する半導体装置くおいて、前記
ポンディングパッド以外の半導体基板表面の全体がポン
ディングパッド位置検出用の光に対して、咳光の反射率
もしくは透過率の少なくともいづれか一方が前記ポンデ
ィングパッドのそれと異なるような被覆膜を設けたこと
を峙徴とする半導体装置。In a semiconductor device having a bonding pad, the entire surface of the semiconductor substrate other than the bonding pad has at least one of reflectance and transmittance of the cough light with respect to the light for detecting the position of the bonding pad. A semiconductor device characterized by having a coating film different from that of a pad.
JP57008162A 1982-01-21 1982-01-21 Semiconductor device Pending JPS58125839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57008162A JPS58125839A (en) 1982-01-21 1982-01-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008162A JPS58125839A (en) 1982-01-21 1982-01-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58125839A true JPS58125839A (en) 1983-07-27

Family

ID=11685631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57008162A Pending JPS58125839A (en) 1982-01-21 1982-01-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58125839A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0436237U (en) * 1990-07-23 1992-03-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0436237U (en) * 1990-07-23 1992-03-26

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