JPH0595034A - Semiconductor manufacturing equipment - Google Patents

Semiconductor manufacturing equipment

Info

Publication number
JPH0595034A
JPH0595034A JP25376891A JP25376891A JPH0595034A JP H0595034 A JPH0595034 A JP H0595034A JP 25376891 A JP25376891 A JP 25376891A JP 25376891 A JP25376891 A JP 25376891A JP H0595034 A JPH0595034 A JP H0595034A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
wafer
illumination
contour
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25376891A
Other languages
Japanese (ja)
Inventor
Yukihiro Okuhara
幸弘 奥原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25376891A priority Critical patent/JPH0595034A/en
Publication of JPH0595034A publication Critical patent/JPH0595034A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To remove a semiconductor chip contour recognition mistake due to scattering of a wafer surface condition or a contour recognition mistake due to halation by patterns having partially a high light-reflectivity in a semiconductor manufacturing equipment of taking out the semiconductor chips one by one from the wafer which is pasted to an adhesive tape and which is fully cut an a basis of one semiconductor chip. CONSTITUTION:When a bad mark of a semiconductor chip 1 is detected, an illumination 2 is applied only from the upper surface of the semiconductor chip 1, and when an contour of the semiconductor chip 1 is recognized, the illumination 2 is applied only from the lower surface of the semiconductor chip 1, whereby the contour of the semiconductor chip can stably be recognized without being completely influenced by scattering of a wafer surface condition or partial patterns having a high light-reflectivity when the contour of the semiconductor chip 1 is recognized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップ単位に切
断されている粘着テープに貼られたウエハより、前記半
導体チップを1個づつ取り出す半導体製造装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus for taking out the semiconductor chips one by one from a wafer attached to an adhesive tape cut into semiconductor chips.

【0002】[0002]

【従来の技術】従来は図3に示すように、照明2はウエ
ハの上面より当て、画像認識用のカメラ3は、反射光を
受けていた。
2. Description of the Related Art Conventionally, as shown in FIG. 3, an illumination 2 is applied from the upper surface of a wafer, and a camera 3 for image recognition receives reflected light.

【0003】[0003]

【発明が解決しようとする課題】しかし、反射光で半導
体チップ1の外形を認識しカケやワレを確認する場合、
半導体チップ1の表面の状態がウエハによって微妙に違
い反射光レベルが変わる事による外形認識ミスや、同一
ウエハ内でも認識している半導体チップの周囲に光の反
射率の高いパターンがあるとハレーションを起こし、半
導体チップ1の外形が検出できないという課題を有して
いた。
However, in the case of recognizing the outer shape of the semiconductor chip 1 by the reflected light and confirming cracks or cracks,
Halation may occur if the surface condition of the semiconductor chip 1 slightly changes depending on the wafer and the reflected light level changes, and if there is a pattern with high light reflectance around the recognized semiconductor chip even within the same wafer. However, there is a problem that the outer shape of the semiconductor chip 1 cannot be detected.

【0004】そこで本発明は、従来のこのような課題を
解決するために、半導体チップの外形検出をする際、照
明をウエハの下面より当て画像認識用のカメラ3に透過
光を受ける事で半導体チップ表面状態のばらつきに影響
せず確実に半導体チップ1の外形認識を行なう事を目的
としている。
Therefore, in order to solve such a conventional problem, the present invention applies a light from the lower surface of the wafer to the transmitted light to the camera 3 for image recognition when detecting the outer shape of the semiconductor chip. The purpose is to reliably recognize the outer shape of the semiconductor chip 1 without affecting the variations in the chip surface state.

【0005】[0005]

【課題を解決するための手段】前述の課題を解決するた
めに本発明の半導体製造装置は、半導体チップ単位に切
断されている粘着テープに貼られたウエハより、前記半
導体チップを1個づつ取り出す半導体製造装置に於て、
前記半導体チップの画像認識の為の照明を前記ウエハの
上面だけでなく下面からも当てる事を特徴とする。
In order to solve the above-mentioned problems, a semiconductor manufacturing apparatus of the present invention takes out the semiconductor chips one by one from a wafer attached to an adhesive tape cut into semiconductor chips. In semiconductor manufacturing equipment,
Illumination for image recognition of the semiconductor chip is applied not only from the upper surface of the wafer but also from the lower surface.

【0006】[0006]

【実施例】以下に本発明の実施例を図面にもとずいて説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0007】図1において、半導体チップ1は粘着テー
プ5に貼られ半導体チップ1個単位にフルカット切断さ
れている。半導体チップ1の電気的特性試験結果が良品
か不良品かを判断するためのバットマーク有無の情報や
半導体チップ1の外形情報などを入手するためのカメラ
3と照明2が設置されている。照明2は半導体チップ1
の上面からと下面から当てられるように半導体チップ1
の上下両方に設置されている。また、突き上げホルダー
7は光を透過する材料で作られている。
In FIG. 1, the semiconductor chip 1 is attached to an adhesive tape 5 and cut into full cuts in units of one semiconductor chip. A camera 3 and an illumination 2 are installed to obtain information on the presence or absence of a bat mark for determining whether the electrical characteristic test result of the semiconductor chip 1 is a good product or a defective product, external shape information of the semiconductor chip 1, and the like. Illumination 2 is semiconductor chip 1
The semiconductor chip 1 so that it can be applied from above and below
It is installed both above and below. The push-up holder 7 is made of a material that transmits light.

【0008】半導体チップ1が良品の場合、突き上げピ
ン4が粘着テープ5を突き破り半導体チップ1を持ち上
げ、コレット6が半導体チップを真空吸着しリードフレ
ームや実装基板などにダイアタッチしたり、もしくは半
導体チップ収納トレイに移送したりする。
When the semiconductor chip 1 is non-defective, the push-up pin 4 breaks through the adhesive tape 5 and lifts the semiconductor chip 1, and the collet 6 vacuum-sucks the semiconductor chip to make a die-attach to a lead frame or a mounting board, or the semiconductor chip. Transfer to storage tray.

【0009】ここで、半導体チップ1のバットマークの
有無を識別する際は、半導体チップ1の下面からの照明
2は消し上面だけから当て反射光から識別する。下面よ
りも同時に照明2から光を当てると半導体チップ1の表
面が暗くなりバットマークの認識ができなくなる。
Here, when identifying the presence or absence of a butt mark on the semiconductor chip 1, the illumination 2 from the lower surface of the semiconductor chip 1 is erased and only the upper surface is illuminated and reflected from the reflected light. When light is applied from the illumination 2 at the same time as the lower surface, the surface of the semiconductor chip 1 becomes dark and the bat mark cannot be recognized.

【0010】半導体チップ1にカケやワレがないことを
確認する外形認識する場合は、バットマーク識別時とは
逆に半導体チップ1の上面から当てる照明2を消し、下
面からの照明2だけにして透過光より情報を取り込む。
In the case of recognizing the outer shape of the semiconductor chip 1 to confirm that there is no chipping or cracking, the illumination 2 applied from the upper surface of the semiconductor chip 1 is turned off and the illumination 2 is applied only from the lower surface, contrary to the bat mark identification. Information is captured from transmitted light.

【0011】半導体チップ上面からだけの照明では、ウ
エハの表面状態がウエハ毎や製造ロットなどでばらつき
反射光のレベルが変わり、上下左右の半導体チップとの
境が見えなくなって外形認識ミスが発生したり、同一ウ
エハ内でも認識している半導体チップの周辺チップに光
の反射率の高いパターンなどが部分的にあるとハレーシ
ョンが起こり同様に上下左右の半導体チップとの境が見
えなくなり外形認識ミスとなる場合が多々ある。
With illumination only from the upper surface of the semiconductor chip, the surface condition of the wafer varies depending on the wafer or manufacturing lot, and the level of reflected light changes, and the boundaries between the upper, lower, left, and right semiconductor chips become invisible, resulting in erroneous outline recognition. Or, if there is a pattern with high light reflectance in the peripheral chip of the semiconductor chip that is recognized even within the same wafer, halation will occur and the boundary between the upper, lower, left and right semiconductor chips will be invisible and the outer shape recognition error will occur. There are many cases.

【0012】外形認識する際、照明を上記のように上面
からでなく半導体チップの下面から当てることで、ウエ
ハの表面状態に影響せず半導体チップの外形認識が可能
となり認識ミスがなくなる。
When recognizing the outer shape, by illuminating the lower surface of the semiconductor chip instead of the upper surface as described above, the outer shape of the semiconductor chip can be recognized without affecting the surface condition of the wafer, and recognition errors are eliminated.

【0013】図2は、本発明の別の実施例で、照明2を
突き上げホルダー7に一体化したものである。光源8は
突き上げホルダー7とは別に設置する。突き上げホルダ
ー7は光を透過する材料である。この実施例では、照明
2の光がチップの真下から当てられ半導体チップ1の外
形がより確実に検出できるようになる。また照明の設置
スペースも効率的である。
FIG. 2 shows another embodiment of the present invention in which the illumination 2 is integrated with the push-up holder 7. The light source 8 is installed separately from the push-up holder 7. The push-up holder 7 is a material that transmits light. In this embodiment, the light of the illumination 2 is applied from directly below the chip, and the outer shape of the semiconductor chip 1 can be detected more reliably. Also, the installation space for lighting is efficient.

【0014】[0014]

【発明の効果】本発明の半導体製造装置は、以上説明し
たように半導体チップのバットマーク検出する際、照明
を半導体チップの上面からだけ当て、半導体チップの外
形認識する際は、半導体チップの下面からだけ照明を当
てる事により、半導体チップの外形認識時に於けるウエ
ハ表面状態のばらつきや光の反射率の高いパターンが部
分的にある事に全く影響せず安定して半導体チップの外
形認識が可能となる。
As described above, the semiconductor manufacturing apparatus of the present invention applies the illumination only from the upper surface of the semiconductor chip when detecting the butt mark of the semiconductor chip, and the lower surface of the semiconductor chip when recognizing the outer shape of the semiconductor chip. By illuminating only from the outside, it is possible to stably recognize the outer shape of the semiconductor chip without affecting the variation of the wafer surface condition and the partial pattern with high light reflectance when recognizing the outer shape of the semiconductor chip. Becomes

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す縦断面図。FIG. 1 is a vertical sectional view showing an embodiment of the present invention.

【図2】本発明の別の実施例を示す縦断面図。FIG. 2 is a vertical sectional view showing another embodiment of the present invention.

【図3】従来の半導体製造装置を示す縦断面図。FIG. 3 is a vertical sectional view showing a conventional semiconductor manufacturing apparatus.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 照明 3 カメラ 4 突き上げピン 5 粘着テープ 6 コレット 7 突き上げホルダー 8 光源 1 semiconductor chip 2 illumination 3 camera 4 push-up pin 5 adhesive tape 6 collet 7 push-up holder 8 light source

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体チップ単位に切断されている粘着テ
ープに貼られたウエハより、前記半導体チップを1個づ
つ取り出す半導体製造装置に於て、前記半導体チップの
画像認識の為の照明を前記ウエハの上面だけでなく下面
からも当てる事を特徴とする半導体製造装置。
1. In a semiconductor manufacturing apparatus for picking up the semiconductor chips one by one from a wafer attached to an adhesive tape cut into semiconductor chip units, the wafer is illuminated with light for image recognition of the semiconductor chips. A semiconductor manufacturing device characterized in that it can be applied not only from the upper surface but also from the lower surface.
JP25376891A 1991-10-01 1991-10-01 Semiconductor manufacturing equipment Pending JPH0595034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25376891A JPH0595034A (en) 1991-10-01 1991-10-01 Semiconductor manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25376891A JPH0595034A (en) 1991-10-01 1991-10-01 Semiconductor manufacturing equipment

Publications (1)

Publication Number Publication Date
JPH0595034A true JPH0595034A (en) 1993-04-16

Family

ID=17255874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25376891A Pending JPH0595034A (en) 1991-10-01 1991-10-01 Semiconductor manufacturing equipment

Country Status (1)

Country Link
JP (1) JPH0595034A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002340963A (en) * 2001-05-14 2002-11-27 Yamaha Fine Technologies Co Ltd Continuity inspection device
US7442420B2 (en) 2001-02-23 2008-10-28 Nippon Kayaku Kabushiki Kaisha Retardation films comprising a UV-curable alignment film and a liquid crystal compound
JP2013115238A (en) * 2011-11-29 2013-06-10 Fuji Mach Mfg Co Ltd Component supply device and component position recognition method
JP2014197697A (en) * 2014-06-04 2014-10-16 上野精機株式会社 Push-up stage of push-up device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7442420B2 (en) 2001-02-23 2008-10-28 Nippon Kayaku Kabushiki Kaisha Retardation films comprising a UV-curable alignment film and a liquid crystal compound
US7445820B2 (en) 2001-02-23 2008-11-04 Nippon Kayaku Kabushiki Kaisha Optical films comprising a UV-curable alignment film and a liquid crystal compound
JP2002340963A (en) * 2001-05-14 2002-11-27 Yamaha Fine Technologies Co Ltd Continuity inspection device
JP2013115238A (en) * 2011-11-29 2013-06-10 Fuji Mach Mfg Co Ltd Component supply device and component position recognition method
JP2014197697A (en) * 2014-06-04 2014-10-16 上野精機株式会社 Push-up stage of push-up device

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