JPH0436237U - - Google Patents

Info

Publication number
JPH0436237U
JPH0436237U JP1990078363U JP7836390U JPH0436237U JP H0436237 U JPH0436237 U JP H0436237U JP 1990078363 U JP1990078363 U JP 1990078363U JP 7836390 U JP7836390 U JP 7836390U JP H0436237 U JPH0436237 U JP H0436237U
Authority
JP
Japan
Prior art keywords
semiconductor device
opening
passivation film
entire surface
external connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990078363U
Other languages
Japanese (ja)
Other versions
JP2513016Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990078363U priority Critical patent/JP2513016Y2/en
Publication of JPH0436237U publication Critical patent/JPH0436237U/ja
Application granted granted Critical
Publication of JP2513016Y2 publication Critical patent/JP2513016Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の第１の実施例を示す斜視図、
第２図は本考案の第２の実施例を示す斜視図、第
３図は従来例を説明するための斜視図である。 FIG. 1 is a perspective view showing a first embodiment of the present invention;
FIG. 2 is a perspective view showing a second embodiment of the present invention, and FIG. 3 is a perspective view illustrating a conventional example.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体チツプのほぼ全面に導電材料から成
る電極を有し、全面をパツシベーシヨン被膜で覆
うと共に外部接続用の開口部を形成した半導体装
置において、 前記パツシベーシヨン被膜に前記導電材料と前
記パツシベーシヨン被膜材料の反射率の差によつ
てパターン認識を行う認識用の開口部を形成した
ことを特徴とする半導体装置。 (2) 前記半導体装置はパワーＭＯＳＦＥＴであ
ることを特徴とする請求項第１項に記載の半導体
装置。[Claims for Utility Model Registration] (1) A semiconductor device having an electrode made of a conductive material on almost the entire surface of a semiconductor chip, the entire surface being covered with a passivation film, and an opening for external connection formed therein, wherein the passivation film has an opening for external connection. A semiconductor device characterized in that a recognition opening is formed for performing pattern recognition based on a difference in reflectance between the conductive material and the passivation film material. (2) The semiconductor device according to claim 1, wherein the semiconductor device is a power MOSFET.
JP1990078363U 1990-07-23 1990-07-23 Semiconductor device Expired - Fee Related JP2513016Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990078363U JP2513016Y2 (en) 1990-07-23 1990-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990078363U JP2513016Y2 (en) 1990-07-23 1990-07-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0436237U true JPH0436237U (en) 1992-03-26
JP2513016Y2 JP2513016Y2 (en) 1996-10-02

Family

ID=31621575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990078363U Expired - Fee Related JP2513016Y2 (en) 1990-07-23 1990-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2513016Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125839A (en) * 1982-01-21 1983-07-27 Nec Corp Semiconductor device
JPH02307235A (en) * 1989-05-23 1990-12-20 Mitsubishi Electric Corp Wire bonding method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125839A (en) * 1982-01-21 1983-07-27 Nec Corp Semiconductor device
JPH02307235A (en) * 1989-05-23 1990-12-20 Mitsubishi Electric Corp Wire bonding method

Also Published As

Publication number Publication date
JP2513016Y2 (en) 1996-10-02

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees