JPS58122738A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent migration of water including impurity and obtain a semiconductor device having excellent characteristic by stacking an Si3N4 film on an SiO2 film at 500 deg.C or less and forming a thin protection film having the structure with an internal stress of 1X10<9>dyn/cm<2> or more as a compressive stress. CONSTITUTION:An SiO2 or PSG film 26b is provided on a field effect transistor (FET) and its internal stress is set to a compressive stress of 1X10<9>dyn/cm<2>. An Si3N4 film 26a is stacked and formed by the plasma CVD method at a temperature of 500 deg.C or less so that a gate electrode 24 does not dissolve and an internal stress of film 26a is set to about 8X10<9>dyn/cm<2>. According to this double structure, a tensile stress of sealing resin is eased, crack is hardly generated, migration of water containing impurity such as Na into elements on a Si substrate 20 can be prevented and element characteristic can also be improved.

Description

[Detailed description of the invention] Technical field of invention The present invention relates to a semiconductor device.

Technical background of the invention and its illumination point A protective film called a passivation film is usually attached to the outermost layer of a semiconductor device in order to improve its reliability. The passivation film must satisfy the following requirements in order to improve the reliability of the device. (2) It has a so-called impurity blocking effect that eliminates water containing alkali metals such as N1, which cause variations in device characteristics during operation. ■
If pinholes, cranks, etc. are present, the aforementioned impurity blocking effect will be lost, so the film must be free of defects.

In ζζ, the occurrence of tardage in the passivation film is facilitated by the tensile stress generated in the resin when semiconductor devices are usually sealed with resin to reduce the cost of the product after assembly. Therefore, it is desirable that the passivation film has a compressive stress that relieves the tensile stress of the sealing resin.
Figure 1 shows an example of a semiconductor device using Pa''Gll as a passivation film. 0 As shown in FIG. 2, this conductor device 4 is made of aluminum via a gate oxide film 4 on the channel region of an NWi semiconductor substrate 1 in which a source 1 and a drain 2 made of p+r11 impurities are formed in predetermined regions. In addition to forming the gate electrode 5, the other exposed surface of the Nyti1 semiconductor substrate 1 is covered with a field oxide film 6, and using the gate electrode 1 as a mask, a hemorrhoid is formed in the area directly under the gate electrode 5, the source 1, and the drain 1. A PgG film 1 is formed on the surface of the impurity region r as shown in FIG. 1 by ion implantation.

However, in this way, P as a passivation film is
In a semiconductor device using the aG film 1, Na of the PBG film 1
Since the blocking effect against alkali metals is weak, Na and the like invade the impurity region r and make it N-type. As a result, variations in the characteristics of the semiconductor device occur. Figure 3 shows the state of this characteristic variation, and the horizontal axis shows the bias temperature (BT, 85 tl ', applying an electric field of 7 V) is displayed in cycles, and the vertical axis shows the change in the oscillation frequency Δfosc (KHz). The curve (1) shows the experimental results. It is shown in

As is clear from the same results, as the number of cycles increases, impurities in moisture invade and the impurity region 1 becomes "shaped", which causes frequency fluctuations.

In order to solve this problem, it is possible to eliminate all pinholes in the passivation film or to increase the concentration of the ir3 impurity region 7. However, the former method is technically almost impossible;
Furthermore, the latter method has the disadvantage of significantly reducing productivity.

OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor device that prevents moisture containing impurities from entering, has excellent device characteristics, and can be easily manufactured.

Summary of the Invention The present invention provides an upper layer made of a silicon nitride film formed at a temperature of 5ooc or less on a lower layer made of an oxide film, and the internal stress of the upper layer is made to be a compressive stress of IX 10"dyn/- or more. By forming the Padgepage impregnated film with a double-layered thin film, the semiconductor device has excellent device characteristics by preventing the intrusion of moisture containing impurities, and is easy to manufacture.

Examples of the invention FIG. 4 is a cross-sectional view of one embodiment of the present invention.

In the figure, 20 is a semiconductor substrate z0, which is a %NIl semiconductor substrate.
A source 11 and a drain 21 made of p''il impurity regions are formed in predetermined regions.

There is a gate on the channel between the source 21 and the drain 21.
A gate electrode 24 made of aluminum, for example, is formed through a diode 114xg. A field oxide film 15 is formed on the drain 22 and the exposed surface of the semiconductor substrate JO. On the field oxide film 25 and the gate electrode @j4, there are an upper layer 3151 and a lower layer 1.
Passivation film 2- consisting of a thin film with a two-layer structure shown in 6b
is formed. Note that :11&, 2111 are P- type impurity regions formed in a region of the semiconductor substrate 20 directly under the gate electrode 24 so as to be connected to the source 11 and the drain 22.

Here, the upper layer 26a of the passivation film 26 is formed of a silicon nitride film with a thickness of about 1.5 μm. The silicon nitride film is heated, for example, by plasma CVD in an atmosphere of 500C or lower to prevent the gate electrode 24 immediately below from melting.
It is preferable to form using the D method. The internal stress of the silicon nitride film is set to be a compressive stress of approximately 8.0 x 10' dyn/-. The lower layer zgb of the pudge vane film 2# is formed of a phosphorus silicate glass film (P2O gland) with a thickness of about tooX. The lower layer J6ib may be formed of a simple oxide film that does not contain phosphorus. Further, the internal stress of the lower layer 26b is set to be a compressive stress of 1x10[deg.]dyn/- or more. In other words, the passivation film 2# has an internal stress of I x 10
” is set to have a compressive stress of dyn/- or more.

When the semiconductor device configured in this way is used, the passivation film 26 is composed of silicon nitride group and P8G.
Jib has a two-layer structure, and the insulation of the silicon nitride film with respect to the field oxide film 25 is compensated by the PEG film forming the lower layer Jib. As a result, as shown at the beginning of curve Iw in FIG. 5, even if a bias voltage of 1 is applied for a long period of time at a high temperature, the value of the threshold voltage vth remains almost constant. On the other hand, as shown by curve Y in the same figure, in a conventional semiconductor device in which the passivation film is formed of a layered silicon nitride film, the value of the threshold voltage vtb suddenly changes within 48 hours of bias application. It can be seen that the bias voltage decreases to 4,000 hours, and then gradually increases up to 4,000 hours in the bias application period after that, indicating that the device characteristics are extremely unstable under high-temperature bias. This is done in order to prevent melting of low melting point electrodes made of aluminum etc.
When silicon nitride is formed at a low temperature below 81N
deviates from the stoichiometric ratio of 8i,N, resulting in an excess of 81, and the excess 81 contained in the form of s i-s i bonds
This is thought to be because the insulation becomes unstable when an electric field is applied due to the behavior of dangling bonds.

The passivation film 26 has an upper layer 26m and a lower layer z.
gb two-layer structure, and the internal stress is set to a compressive stress of I x 10" dyn /- or more, as shown by curve # (X') in Fig. 6.
It can be seen that the frequency of crack occurrence in the PSG film of the lower layer 26b is almost non-existent.

On the other hand, as shown by the white # (Y) in the same figure, in a passivation film made of P8Gg with a single layer structure, cracks still occur even if the internal stress is set to a compressive stress of lX10"dyn/- or more. It turns out that we cannot completely eliminate it.

In this way, the passivation film 26 consists of an upper layer xtta made of a silicon nitride film and a lower layer jll made of a PSG film.
Since it adopts a two-layer structure consisting of B and B, it can improve insulation and almost prevent the occurrence of cracks.
It is possible to prevent the intrusion into an element formed in the same manner as to improve the element characteristics. This is clear from the results of the change in the number of test cycles and the oscillation station wave number of PC and BT, which are indicated by the characteristic line (m) in Figure 3.Also, in order to improve the device characteristics, P- Mold impurity region 211
, 218 is not required, so it can be easily manufactured using a simplified process.

In the embodiment, an MO811 element was formed on the semiconductor substrate 2o, but it is of course possible to form any desired element such as a bipolar anti-node element in addition to the semiconductor substrate 2o.

As described in detail, the semiconductor device according to the present invention has excellent device characteristics by preventing the intrusion of moisture containing impurities, and has remarkable effects such as being easy to manufacture. It is.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a conventional semiconductor device, and FIG.
The figure is an explanatory diagram showing the manufacturing method of the regenerative conductor device, Figure 3 is a characteristic diagram showing the relationship between the change in emission frequency, PCT, and the number of test cycles for one piece, and Figure 4 is an illustration of the method of manufacturing the regenerative conductor device. A cross-sectional view of the example, FIG. 5 is a characteristic diagram showing the relationship between threshold voltage and bias application time, and FIG. 6 is a characteristic diagram showing the relationship between the crack occurrence frequency and P2
FIG. 3 is a characteristic diagram showing the relationship with stress of an O film. 20... Semiconductor substrate, 21... Source, 22...
Drain, 211, 238... impurity region srs...
・Gate oxide film, 24... Gate electrode, 25... Field oxide film, 26... Passivation film, 1#
G... Upper layer, 26b... Lower layer, 10... Semiconductor device O Applicant's agent Patent attorney Takehiko Suzue Figure 4 30 Figure 5

Claims (1)

[Claims] In a semiconductor device comprising a semiconductor substrate with a predetermined conductive pattern on which a desired element is formed, and a passivation film formed on the element to cover the element, the passivation film is replaced with a silicon nitride film. and a lower layer consisting of an oxide film, and the upper layer and the lower layer have a compressive internal stress of 1 x 10" dyn/- or more. Semiconductor equipment.