KR970052024A - SOH eye substrate manufacturing method - Google Patents

SOH eye substrate manufacturing method Download PDF

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Publication number
KR970052024A
KR970052024A KR1019950069481A KR19950069481A KR970052024A KR 970052024 A KR970052024 A KR 970052024A KR 1019950069481 A KR1019950069481 A KR 1019950069481A KR 19950069481 A KR19950069481 A KR 19950069481A KR 970052024 A KR970052024 A KR 970052024A
Authority
KR
South Korea
Prior art keywords
wafer
forming
oxide film
soi substrate
doped oxide
Prior art date
Application number
KR1019950069481A
Other languages
Korean (ko)
Inventor
김재갑
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950069481A priority Critical patent/KR970052024A/en
Priority to TW085115677A priority patent/TW310458B/zh
Priority to DE19653632A priority patent/DE19653632B4/en
Priority to JP8357094A priority patent/JPH1032321A/en
Priority to GB9626954A priority patent/GB2309584A/en
Priority to CN96123934A priority patent/CN1078739C/en
Publication of KR970052024A publication Critical patent/KR970052024A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Abstract

본 발명은 에스 오 아이(이하 SOI : silicon on insulator) 기판 제조방법에 관한 것으로, 특히 SOI의 기판의 접착 공정시 파티클에 의한 결함을 방지할 수 있는 SOI 기판 제조방법에 관한 것으로, 본 발명에 의하면 표면에 절연막이 형성된 두 웨이퍼를 부착하여 형성하는 SOI 기판 형성시, 표면 절연막을 도프트 산화막을 양 웨이퍼 표면에 형성하여 고온의 접착공정시 플로우 현상을 유발시키어 접착시 표면에 잔존하는 파티클을 매몰시키므로써, 표면이 균일한 SOI 기판을 형성하고, 이로써, 소자의 제조 수율을 향상시킬 수 있다.The present invention relates to a method for manufacturing a silicon on insulator (SOI) substrate, and more particularly, to a method for manufacturing an SOI substrate capable of preventing defects caused by particles during the bonding process of the substrate. When forming an SOI substrate formed by attaching two wafers with an insulating film on the surface, a surface insulating film is formed on both wafer surfaces to induce a flow phenomenon during the high temperature bonding process, thereby buried particles remaining on the surface during bonding. In addition, an SOI substrate having a uniform surface can be formed, whereby the manufacturing yield of the device can be improved.

Description

에스 오 아이 기판 제조방법SOH eye substrate manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (가) 내지 (다)는 본 발명에 에스 오 아이 기판 제조방법을 설명하기 위한 각 제조공정에 있어서의 요부 단면도.2 (a) to (c) are cross-sectional views of the main parts in each manufacturing process for explaining the method of manufacturing the SOH eye substrate to the present invention.

Claims (9)

소자 형성용 웨이퍼의 핸들링 웨이퍼를 부착하여 형성하는 SOI 기판 제조방법에 있어서, 상기 소자 형성용 웨이퍼와 핸들링 웨이퍼의 접착 공정 이전에 상기 소자 형성용 웨이퍼 상부에 도프트 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 SOI 기판 제조방법.An SOI substrate manufacturing method for attaching and forming a handling wafer of a device forming wafer, the method comprising: forming a doped oxide film on the device forming wafer prior to the bonding process between the device forming wafer and the handling wafer; SOI substrate manufacturing method characterized by. 제1항에 있어서, 상기 소자 형성용 웨이퍼와 핸들링 웨이퍼의 접착 공정 이전에 핸들링 웨이퍼 상부에도 도프트 산화막을 형성하는 단계를 부가적으로 포함하는 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, further comprising forming a doped oxide layer on the handling wafer prior to the bonding process between the device forming wafer and the handling wafer. 제1항에 있어서, 상기 소자 형성용 웨이퍼 상부에 불순물 도프트 산화막을 형성하는 단계 이전에 불순물 확산 방지막을 형성하는 단계를 형성하는 것을 특징으로 하는 SOI 기판 제조방법.The method of manufacturing an SOI substrate according to claim 1, further comprising forming an impurity diffusion barrier layer before forming an impurity doped oxide film on the device forming wafer. 제1항에 있어서, 상기 불순물 확산 방지막은 질화막, 비도핑 산화막, 질화막과 비도핑 산화막 중 선택되는 하나의 막인 것을 특징으로하는 하는 SOI 기판 제조방법.The method of claim 1, wherein the impurity diffusion barrier layer is one of a nitride film, an undoped oxide film, a nitride film, and an undoped oxide film. 제1항에 있어서, 상기 도프트 산화막은 PSG, BSG, BPSG 중 선택되는 하나의 막인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein the doped oxide film is one of PSG, BSG, and BPSG. 제1항에 있어서, 상기 도프트 산화막은 저온에서 증착하는 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein the doped oxide film is deposited at a low temperature. 제5항 또는 제6항에 있어서, 상기 도프트 산화막이 PSG인 경우, 실리콘 웨이퍼와 핸들링 웨이퍼간의 접착 온도는 900 내지 1000℃인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 5 or 6, wherein when the doped oxide film is PSG, the adhesion temperature between the silicon wafer and the handling wafer is 900 to 1000 ° C. 제5항 또는 제6항에 있어서, 상기 도프트 산화막이 BSG 또는 BPSG인 경우, 실리콘 웨이퍼와 핸들링 웨이퍼간의 접착 온도는 800 내지 950℃인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 5 or 6, wherein when the doped oxide film is BSG or BPSG, the adhesion temperature between the silicon wafer and the handling wafer is 800 to 950 ° C. 소자 형성용 웨이퍼와 핸들링 웨이퍼를 부착하여 형성하는 SOI 기판 제조방법에 있어서, 상기 소자 형성용 웨이퍼와 핸들링 웨이퍼 접착 공정 이전에 상기 핸들링 웨이퍼 상부에 도프트 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 SOI 기판 제조방법.An SOI substrate manufacturing method for attaching and forming a device forming wafer and a handling wafer, the method comprising: forming a doped oxide layer on the handling wafer prior to the bonding process between the device forming wafer and the handling wafer; SOI substrate manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069481A 1995-12-30 1995-12-30 SOH eye substrate manufacturing method KR970052024A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950069481A KR970052024A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method
TW085115677A TW310458B (en) 1995-12-30 1996-12-19
DE19653632A DE19653632B4 (en) 1995-12-30 1996-12-20 Method of making a silicon-on-insulator substrate
JP8357094A JPH1032321A (en) 1995-12-30 1996-12-26 Soi substrate and its manufacture
GB9626954A GB2309584A (en) 1995-12-30 1996-12-27 Forming S.O.I. substrates
CN96123934A CN1078739C (en) 1995-12-30 1996-12-30 Silicon-on-insulator substrate and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069481A KR970052024A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method

Publications (1)

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KR970052024A true KR970052024A (en) 1997-07-29

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JP (1) JPH1032321A (en)
KR (1) KR970052024A (en)
CN (1) CN1078739C (en)
DE (1) DE19653632B4 (en)
GB (1) GB2309584A (en)
TW (1) TW310458B (en)

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KR100359681B1 (en) * 2000-03-15 2002-11-04 오정훈 Method to manufacture imitation metal jewel
US6541861B2 (en) 2000-06-30 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure
AU2002360825A1 (en) * 2002-05-31 2003-12-19 Advanced Micro Devices, Inc. Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back side
KR100511656B1 (en) * 2002-08-10 2005-09-07 주식회사 실트론 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
JP5194508B2 (en) * 2007-03-26 2013-05-08 信越半導体株式会社 Manufacturing method of SOI wafer
CN101916761B (en) * 2010-07-20 2012-07-04 中国科学院上海微系统与信息技术研究所 Conductive layer under SOI oxygen buried layer and manufacturing process thereof
JP2016100566A (en) * 2014-11-26 2016-05-30 トヨタ自動車株式会社 Soi wafer manufacturing method and soi wafer
US9515072B2 (en) * 2014-12-26 2016-12-06 Taiwan Semiconductor Manufacturing Company Ltd. FinFET structure and method for manufacturing thereof
CN105392093B (en) * 2015-12-03 2018-09-11 瑞声声学科技(深圳)有限公司 The manufacturing method of microphone chip
CN105392089A (en) * 2015-12-03 2016-03-09 瑞声声学科技(深圳)有限公司 Composite layer structure and manufacture method thereof
EP3758050A1 (en) * 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

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US4641173A (en) * 1985-11-20 1987-02-03 Texas Instruments Incorporated Integrated circuit load device
US5387555A (en) * 1992-09-03 1995-02-07 Harris Corporation Bonded wafer processing with metal silicidation
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JP3237888B2 (en) * 1992-01-31 2001-12-10 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same

Also Published As

Publication number Publication date
CN1078739C (en) 2002-01-30
GB2309584A (en) 1997-07-30
DE19653632A1 (en) 1997-07-03
JPH1032321A (en) 1998-02-03
GB9626954D0 (en) 1997-02-12
TW310458B (en) 1997-07-11
DE19653632B4 (en) 2004-08-26
CN1162834A (en) 1997-10-22

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