JPH03212969A - Ferroelectric device - Google Patents

Ferroelectric device

Info

Publication number
JPH03212969A
JPH03212969A JP873090A JP873090A JPH03212969A JP H03212969 A JPH03212969 A JP H03212969A JP 873090 A JP873090 A JP 873090A JP 873090 A JP873090 A JP 873090A JP H03212969 A JPH03212969 A JP H03212969A
Authority
JP
Japan
Prior art keywords
electrode
film
ferroelectric
si3n4
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP873090A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP873090A priority Critical patent/JPH03212969A/en
Publication of JPH03212969A publication Critical patent/JPH03212969A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the use of a costly Pt electrode and to prevent a deterioration by a method wherein electrodes are formed on one main face or two main faces of a ferroelectric film via Si3N4. CONSTITUTION:A C-MOS semiconductor substrate is composed of the following: an Si substrate 1; a P-well or an N-well 2; a source 3; a drain 4; SiO2 5; a gate 6; and a glass (1) 7. Poly-Si, Ti, W, TiN, WSi, Al or the like other than Pt is formed as a lower-part electrode 8 on the substrate by a sputtering method or the like. A film of Si3N4 (1) 9 is formed on the electrode 8 by a plasma CVD method or the like. After that, a ferroelectric material 10 such as PZT, BaTiO3, Pb5Ge3O11, Bi4Ti3O12 or the like is formed as a film by a sputtering method or a sol-gel method. In addition, Si3N4 (2) 11 is formed as a lower-part electrode. After that, an upper-part electrode 12 is formed in the same manner. A metal electrode of Al 14 or the like is connected to the electrodes 8, 12 via a glass (2) 13. Thereby, it is possible to prevent deterioration economically.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は強誘電体装置の構造に係り、主として軍使材料
と強誘電体膜界面構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the structure of a ferroelectric device, and mainly relates to the interfacial structure between a military material and a ferroelectric film.

[従来の技術] 従来、P Z T (P b −Z r −T i f
j/l化物)に代表される強誘電体装置を例えば半導体
装置に組み込む場合には、pt電電膜膜上PZT膜等の
強誘電体膜を形成し、更に上部電極もPtt使膜を用い
る場合もあった。
[Prior art] Conventionally, P Z T (P b −Z r −T i f
For example, when a ferroelectric device such as a ferroelectric device (J/L compound) is incorporated into a semiconductor device, a ferroelectric film such as a PZT film is formed on a PT film, and a Ptt film is also used for the upper electrode. There was also.

[発明が解決しようとする課題] しかし、上記従来技術によると強誘電体膜の少な(とも
−主面には高価なpt電極を用いなければならないと言
5課題があった。
[Problems to be Solved by the Invention] However, the above-mentioned prior art has five problems, including the need to use an expensive PT electrode on the main surface of the ferroelectric film.

本発明は、かかる従来技術の課題を解決し、Pt’を極
を用いな(ても良い強誘電体装置の強誘電体と電極との
界面構造を提供する事を目的とする。
It is an object of the present invention to solve the problems of the prior art and to provide an interface structure between a ferroelectric and an electrode of a ferroelectric device that does not use Pt' as a pole.

[課題を解決するための手段] 上記課題を解決するために、本発明は、強誘電体装置に
関し、強誘電体膜の一主面又は二主面にSi3N、を介
してitmを形成する手段を取る。
[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a ferroelectric device, and provides means for forming itm on one or two main surfaces of a ferroelectric film via Si3N. I take the.

[実施例コ 以下、実施例により本発明を詳述する。[Example code] Hereinafter, the present invention will be explained in detail with reference to Examples.

第1図は本発明の一実施例を示すC−MO3半導体装置
に組み込んだ強誘電体装置の断面図である。
FIG. 1 is a sectional view of a ferroelectric device incorporated in a C-MO3 semiconductor device showing an embodiment of the present invention.

いま、O−M OS半導体基板が、81基板1Pウエル
又はNウェル2.ソース3.ドレイン4、Si0,5.
ゲート6及びガラス(1)7から成り該基板上に下部電
極8としてpt以外のPO1yS1やTi、W、TiN
、WSi、At等をスパッタ法等により形成し、該下部
電極8の上にプラズマGIVD法等により5isN+(
1)9の膜を形成後、I’ZTやBaTiO3、Pb5
Ge30H。
Now, the O-MOS semiconductor substrate is 81 substrates 1P well or N well 2. Source 3. Drain 4, Si0,5.
It consists of a gate 6 and glass (1) 7, and a lower electrode 8 on the substrate is made of PO1yS1 other than pt, Ti, W, TiN.
, WSi, At, etc. are formed by sputtering or the like, and 5isN+(
1) After forming the film 9, I'ZT, BaTiO3, Pb5
Ge30H.

B14Ti、O,、等の強誘電体10をスパッタ法やゾ
ル・ゲル法により膜として形成し、更に、S i3N、
 (2111を形成後上部電極12を下部電極11と同
様の方法、材料にて形成し、ガラス(2)13を介して
At、、等の金属電極を前記下部電極8及び下部電極1
2と接続して成る。
A ferroelectric material 10 such as B14Ti, O, etc. is formed as a film by sputtering or sol-gel method, and then Si3N,
(After forming 2111, the upper electrode 12 is formed using the same method and material as the lower electrode 11, and a metal electrode such as At, etc. is connected to the lower electrode 8 and the lower electrode 1 through the glass (2) 13.
It is connected to 2.

本発明によるSi3N4膜の作用は強誘電体膜とtt極
との反応による強誘電体膜特性の劣化、とりわけリーク
電流の防止であり、Si3N、膜と強誘電体膜との反応
はptと強誘電体膜との反応と同等又はそれ以下に押え
ることができる作用がある。
The action of the Si3N4 film according to the present invention is to prevent deterioration of the ferroelectric film properties, especially leakage current, due to the reaction between the ferroelectric film and the tt electrode, and the reaction between the Si3N film and the ferroelectric film is to It has the effect of suppressing the reaction with the dielectric film to a level equal to or lower than that.

[発明の効果コ 本発明により、低コストで劣化の無い強誘電体装置を提
供することができる効果がある。
[Effects of the Invention] The present invention has the effect of providing a ferroelectric device at low cost and free from deterioration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す0−MOS半導体装置
に組み込んだ強誘電体装置の断面図である。 1・・・・・・・・・S1基板 2・・・・・・・・・Pウェル又はNウェル3・・・・
・・・・・ソース 4・・・・・・・・・ドレイン 5・・・・・・・・・S i 0゜ 6・・・・・・・・・ゲート 7・・・・・・・・・ガラス(1) 8・・・・・・・・・下部電極 9・・・・・・・・・Si3N、(2110・・・・・
・強誘電体 1 ・・・・・・ Si 3N4 2・・・・・・上部電極 3・・・・・・ガラス(2) 4・・・・・・At
FIG. 1 is a cross-sectional view of a ferroelectric device incorporated in an 0-MOS semiconductor device showing one embodiment of the present invention. 1...S1 substrate 2...P well or N well 3...
...Source 4...Drain 5...S i 0゜6...Gate 7...・・Glass (1) 8 ・・・・・ Lower electrode 9 ・・・・・ Si3N, (2110 ・・・
・Ferroelectric material 1...Si 3N4 2...Top electrode 3...Glass (2) 4...At

Claims (1)

【特許請求の範囲】[Claims]  強誘電体膜の一主面又は二主面にはSi_3N_4膜
を介して電極が形成されて成る事を特徴とする強誘電体
装置。
A ferroelectric device characterized in that an electrode is formed on one or two main surfaces of a ferroelectric film via a Si_3N_4 film.
JP873090A 1990-01-18 1990-01-18 Ferroelectric device Pending JPH03212969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP873090A JPH03212969A (en) 1990-01-18 1990-01-18 Ferroelectric device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP873090A JPH03212969A (en) 1990-01-18 1990-01-18 Ferroelectric device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP11126080A Division JP2000036565A (en) 1999-05-06 1999-05-06 Ferroelectric apparatus
JP2000127806A Division JP2000307072A (en) 2000-01-01 2000-04-27 Ferroelectric device

Publications (1)

Publication Number Publication Date
JPH03212969A true JPH03212969A (en) 1991-09-18

Family

ID=11701071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP873090A Pending JPH03212969A (en) 1990-01-18 1990-01-18 Ferroelectric device

Country Status (1)

Country Link
JP (1) JPH03212969A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100231604B1 (en) * 1996-12-20 1999-11-15 김영환 Manufacturing method of capacitor of semiconductor device
KR100398569B1 (en) * 2000-12-19 2003-09-19 주식회사 하이닉스반도체 Method for manufactruing capacitor in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100231604B1 (en) * 1996-12-20 1999-11-15 김영환 Manufacturing method of capacitor of semiconductor device
KR100398569B1 (en) * 2000-12-19 2003-09-19 주식회사 하이닉스반도체 Method for manufactruing capacitor in semiconductor device

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