JPH0684886A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0684886A
JPH0684886A JP23610492A JP23610492A JPH0684886A JP H0684886 A JPH0684886 A JP H0684886A JP 23610492 A JP23610492 A JP 23610492A JP 23610492 A JP23610492 A JP 23610492A JP H0684886 A JPH0684886 A JP H0684886A
Authority
JP
Japan
Prior art keywords
region
semiconductor substrate
film
electrode
polyimide resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23610492A
Other languages
Japanese (ja)
Inventor
Haruhiko Yamamoto
治彦 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP23610492A priority Critical patent/JPH0684886A/en
Publication of JPH0684886A publication Critical patent/JPH0684886A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To improve reliability of an element and to improve humidity resistance life thereof by improving adhesion of a protection polyimide resin film. CONSTITUTION:A collector region 2, a base region 3 and an emitter region 4 are formed inside a semiconductor substrate 2. An insulation film 5 consisting of a thermal oxide SiO2 film, a base electrode 3a and an emitter electrode 4a are formed on a surface of the semiconductor substrate 1. V-shaped grooves 7 are formed on a surface of the semiconductor substrate 1 to enclose the base region 3 and the emitter region 4. A polyimide region film 6 is laminated on the insulation film 5, the base electrode 3a and the emitter electrode 4a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

【0002】[0002]

【従来の技術】半導体装置として、半導体素子が形成さ
れた半導体基板表面が保護用ポリイミド系樹脂膜で覆わ
れたものが最近多く用いられるようになった。ポリイミ
ド系樹脂膜は、SiO2 やSiNなどの無機絶縁膜に比
べ、欠陥が少ない、厚膜形成が可能である、凹凸のある
基板上に平坦な膜形成が容易であるなどのメリットがあ
る。
2. Description of the Related Art Recently, a semiconductor device in which a semiconductor substrate surface on which a semiconductor element is formed is covered with a protective polyimide resin film has been widely used. The polyimide-based resin film has advantages such as fewer defects, a thick film can be formed, and a flat film can be easily formed on an uneven substrate as compared with an inorganic insulating film such as SiO 2 or SiN.

【0003】図3は、PNPトランジスタが形成された
半導体基板表面を保護用ポリイミド樹脂で覆った半導体
装置を示すものである。この素子は、半導体基板21内
にコレクタ領域22、ベース領域23及びエミッタ領域
24が形成されているとともに、半導体基板21表面に
は、熱酸化SiO2 膜からなる絶縁膜25、ベース電極
23a、エミッタ電極24aが形成されている(コレク
タ電極は図示外における半導体基板21表面あるいは裏
面に形成されている)。そして、絶縁膜25や各電極2
3a,24aを覆うようにポリイミド樹脂膜26が形成
されている。このポリイミド樹脂膜26は、半導体素子
の機械的ストレスからの保護や耐湿性向上のために設け
られるものである。
FIG. 3 shows a semiconductor device in which the surface of a semiconductor substrate on which a PNP transistor is formed is covered with a protective polyimide resin. In this element, a collector region 22, a base region 23 and an emitter region 24 are formed in a semiconductor substrate 21, and an insulating film 25 made of a thermally oxidized SiO 2 film, a base electrode 23a, an emitter are formed on the surface of the semiconductor substrate 21. An electrode 24a is formed (the collector electrode is formed on the front surface or the back surface of the semiconductor substrate 21 not shown). Then, the insulating film 25 and each electrode 2
A polyimide resin film 26 is formed so as to cover 3a and 24a. The polyimide resin film 26 is provided to protect the semiconductor element from mechanical stress and improve moisture resistance.

【0004】このPNPトランジスタを樹脂封止する場
合、半導体基板21を外部電極取り出し用リードフレー
ム27に固着し、金あるいはアルミのワイヤー28でリ
ードフレーム27と各電極を接続し、最後に封止樹脂2
9で封止する。
When the PNP transistor is sealed with a resin, the semiconductor substrate 21 is fixed to the lead frame 27 for extracting external electrodes, the lead frame 27 and each electrode are connected with a wire 28 of gold or aluminum, and finally the sealing resin is used. Two
Seal with 9.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記半
導体装置においては、温度変化を受け、また高湿な雰囲
気に曝された場合、封止樹脂29と半導体基板21との
熱膨張係数の差あるいは吸湿による樹脂の膨潤に起因し
て封止樹脂29と半導体基板21の界面に隙間が発生す
る。外気に含まれる水分はこの隙間を通じて浸入し、半
導体基板21の表面層まで達する。
However, in the above semiconductor device, when the semiconductor device is exposed to a temperature change and a high humidity atmosphere, the difference in coefficient of thermal expansion between the sealing resin 29 and the semiconductor substrate 21 or moisture absorption. Due to the swelling of the resin due to, a gap is generated at the interface between the sealing resin 29 and the semiconductor substrate 21. Moisture contained in the outside air enters through the gap and reaches the surface layer of the semiconductor substrate 21.

【0006】一般にシリコン、二酸化シリコン等の非金
属材料と樹脂との密着性は、水の介入によって著しく低
下する欠点がある。従って、この隙間を通して半導体基
板21の表面まで達した水は、半導体基板21及び絶縁
膜25とポリイミド樹脂膜26との密着性を低下させ、
ベース電極23aにまで達する。以上の結果、水の介在
によりベース・コレクタ間の逆耐圧不良が起こり、半導
体装置としての機能を果たさなくなる。
In general, the adhesion between non-metal materials such as silicon and silicon dioxide and the resin is remarkably lowered by the intervention of water. Therefore, the water reaching the surface of the semiconductor substrate 21 through this gap reduces the adhesion between the semiconductor substrate 21 and the insulating film 25 and the polyimide resin film 26,
It reaches the base electrode 23a. As a result, the reverse breakdown voltage between the base and collector occurs due to the presence of water, and the semiconductor device does not function as a semiconductor device.

【0007】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、保護用ポリイミド系樹脂
膜の密着性が低下せず、信頼性の高い半導体装置を提供
することにある。
The present invention has been made in view of the above problems, and an object thereof is to provide a highly reliable semiconductor device in which the adhesion of the protective polyimide resin film does not deteriorate. .

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
本発明は、半導体素子が形成された半導体基板表面に前
記半導体素子を取り囲む溝を形成するとともに、該溝及
び前記半導体素子をポリイミド系の樹脂膜で被覆したこ
とを特徴とするものである。
In order to solve the above problems, the present invention forms a groove surrounding the semiconductor element on the surface of the semiconductor substrate on which the semiconductor element is formed, and the groove and the semiconductor element are made of a polyimide-based material. It is characterized by being covered with a resin film.

【0009】半導体素子としては、トランジスタ(例え
ば、バイポーラトランジスタ、MOSトランジスタ
等)、サイリスタ(例えば、静電誘導サイリスタ等)を
例示するが、これらに限るものではない。また、複数の
半導体素子が一つの半導体基板に形成された集積回路で
もよい。
Examples of the semiconductor element include a transistor (for example, a bipolar transistor, a MOS transistor, etc.) and a thyristor (for example, an electrostatic induction thyristor), but the semiconductor element is not limited to these. Further, an integrated circuit in which a plurality of semiconductor elements are formed on one semiconductor substrate may be used.

【0010】溝の形状はV型あるいはU型等に形成さ
れ、溝の深さは10〜20μm程度である。溝は周知の
フォトリソグラフ技術及び選択エッチング技術によって
形成される。
The shape of the groove is V-shaped or U-shaped, and the depth of the groove is about 10 to 20 μm. The groove is formed by the well-known photolithographic technique and selective etching technique.

【0011】ポリイミド系樹脂としては、例えば、厚み
約5〜7μmのポリイミド樹脂膜が使われる。何らかの
変成がなされたポリイミド系樹脂を用いてもよい。ポリ
イミド樹脂膜は、例えば、感光性液状ポリイミド樹脂組
成物を半導体基板に塗布し、プリベークを経た後、ボン
ディングパッドのパターン形成のための露光・現像・リ
ンス処理を行い、ポストベークすることで形成される。
As the polyimide resin, for example, a polyimide resin film having a thickness of about 5 to 7 μm is used. A modified polyimide resin may be used. The polyimide resin film is formed by, for example, applying a photosensitive liquid polyimide resin composition to a semiconductor substrate, performing pre-baking, then performing exposure / development / rinsing processing for pattern formation of bonding pads, and post-baking. It

【0012】[0012]

【作用】本発明に係る半導体装置では、半導体基板表面
に半導体素子を取り囲む溝が形成されているため、ポリ
イミド系樹脂と半導体基板の密着する部分の面積が増大
する。すなわち、トータルとしてのポリイミド系樹脂と
半導体基板との密着力が大きくなる。
In the semiconductor device according to the present invention, since the groove surrounding the semiconductor element is formed on the surface of the semiconductor substrate, the area of the contact portion between the polyimide resin and the semiconductor substrate increases. That is, the total adhesion between the polyimide resin and the semiconductor substrate is increased.

【0013】また、水分の浸入経路は、主としてポリイ
ミド系樹脂と半導体基板との界面のチップ端部からチッ
プ中央部への経路が考えられるが、溝が形成されている
ため、チップ端部から素子形成部までの距離が長くな
り、前述のように、たとえ高温高湿の雰囲気に曝し、水
分が浸入しても、素子特性に影響を与える部分へ水分が
達するまでに時間がかかり、従来に比較して耐湿寿命が
向上する。
Further, as a water infiltration route, a route from the chip edge portion to the chip central portion mainly at the interface between the polyimide resin and the semiconductor substrate can be considered. However, since the groove is formed, the chip edge portion leads to the element. As the distance to the formation part becomes longer, as described above, it takes time for the water to reach the part that affects the device characteristics, even if it is exposed to the high temperature and high humidity atmosphere and the water infiltrates. The moisture-proof life is improved.

【0014】[0014]

【実施例】図1は、本発明の一実施例に係るプレーナ型
PNPトランジスタ素子をもつ半導体装置を示すもので
ある。
1 shows a semiconductor device having a planar type PNP transistor element according to an embodiment of the present invention.

【0015】この半導体装置は、半導体基板1内にコレ
クタ領域(P領域)2、ベース領域(N領域)3及びエ
ミッタ領域(P領域)4が形成されているとともに、半
導体基板1表面には、熱酸化SiO2 膜からなる絶縁膜
5、ベース電極3a、エミッタ電極4aが形成されてい
る(コレクタ電極は図示外における半導体基板1表面あ
るいは裏面に形成されている)。
In this semiconductor device, a collector region (P region) 2, a base region (N region) 3 and an emitter region (P region) 4 are formed in a semiconductor substrate 1, and the surface of the semiconductor substrate 1 is An insulating film 5 made of a thermally oxidized SiO 2 film, a base electrode 3a, and an emitter electrode 4a are formed (the collector electrode is formed on the front surface or the back surface of the semiconductor substrate 1 not shown).

【0016】そして、半導体基板1表面にベース領域3
及びエミッタ領域4を取り囲むようにV型の溝7が形成
され、絶縁膜5、ベース電極3a、エミッタ電極4aの
上にポリイミド樹脂膜6が積層されている。この溝7
は、(100)シリコン基板に対し、温度70〜80℃
で水酸化カリウム・水・エチルアルコール・イソプロピ
ルアルコールの混合溶液をエッチング液として用いて、
シリコン酸化膜をマスクとして形成される。本実施例で
は45分間エッチングし、深さ約20μmのV溝を形成
した。
The base region 3 is formed on the surface of the semiconductor substrate 1.
Further, a V-shaped groove 7 is formed so as to surround the emitter region 4, and a polyimide resin film 6 is laminated on the insulating film 5, the base electrode 3a and the emitter electrode 4a. This groove 7
Is 70 to 80 ° C. for a (100) silicon substrate.
With a mixed solution of potassium hydroxide / water / ethyl alcohol / isopropyl alcohol as an etching solution,
It is formed using the silicon oxide film as a mask. In this example, etching was performed for 45 minutes to form a V groove having a depth of about 20 μm.

【0017】次に、図2は本発明の異なる実施例を示す
もので、表面ゲート型静電誘導サイリスタ素子をもつ半
導体装置を示す。
Next, FIG. 2 shows a different embodiment of the present invention, showing a semiconductor device having a surface gate type electrostatic induction thyristor element.

【0018】この半導体装置は、半導体基板11の裏面
側にアノード領域(P領域)12及びアノード電極12
aを備え、半導体基板11の表面側にカソード領域(N
領域)13、ゲート領域(P領域)14、カソード電極
13a及びゲート電極14aを備えるとともに、カソー
ド領域13とアノード領域12の間に高比抵抗領域(N
領域)18を備えた表面ゲート型サイリスタ構造を有す
る。半導体基板11表面には、熱酸化SiO2 膜からな
る絶縁膜15が形成されている。
This semiconductor device has an anode region (P region) 12 and an anode electrode 12 on the back surface side of the semiconductor substrate 11.
a, the cathode region (N
Region 13), a gate region (P region) 14, a cathode electrode 13a and a gate electrode 14a, and a high specific resistance region (N
Region 18) and has a surface gate type thyristor structure. An insulating film 15 made of a thermally oxidized SiO 2 film is formed on the surface of the semiconductor substrate 11.

【0019】そして、ゲート領域14とカソード領域1
3を取り囲むようにV溝17が形成され、絶縁膜15、
カソード電極13a、ゲート電極14aの上にポリイミ
ド樹脂膜16が積層されている。
Then, the gate region 14 and the cathode region 1
3, a V groove 17 is formed so as to surround the insulating film 15,
A polyimide resin film 16 is laminated on the cathode electrode 13a and the gate electrode 14a.

【0020】なお、本発明は上記実施例に限定されるも
のでないのは勿論であり、例えば、溝7,17の形状は
U型であってもトレンチ型であってもよい。また、溝
7,17も複数設けてもよい。
Of course, the present invention is not limited to the above-described embodiment, and the grooves 7 and 17 may be U-shaped or trench-shaped, for example. Also, a plurality of grooves 7 and 17 may be provided.

【0021】[0021]

【発明の効果】本発明は上記のように、半導体基板表面
に半導体素子を取り囲む溝を形成したことにより、ポリ
イミド系樹脂膜と半導体基板の密着性が向上し、信頼性
の高い半導体装置を提供することができる。また、高湿
雰囲気に曝したとき、水分の素子部への浸入経路が長く
なり、耐湿寿命を大幅に改善することができる。
As described above, the present invention provides a highly reliable semiconductor device in which the adhesion between the polyimide resin film and the semiconductor substrate is improved by forming the groove surrounding the semiconductor element on the surface of the semiconductor substrate. can do. Further, when exposed to a high humidity atmosphere, the path of moisture penetration into the element portion becomes long, and the moisture resistance life can be greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す概略断面図である。FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

【図2】本発明の異なる実施例を示す概略断面図であ
る。
FIG. 2 is a schematic sectional view showing a different embodiment of the present invention.

【図3】従来例を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

1,11 半導体基板 6,16 ポリイミド系樹脂膜 7,17 溝 1,11 Semiconductor substrate 6,16 Polyimide resin film 7,17 Groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子が形成された半導体基板表面
に前記半導体素子を取り囲む溝を形成するとともに、該
溝及び前記半導体素子をポリイミド系の樹脂膜で被覆し
たことを特徴とする半導体装置。
1. A semiconductor device, comprising: forming a groove surrounding the semiconductor element on the surface of a semiconductor substrate having the semiconductor element formed thereon; and coating the groove and the semiconductor element with a polyimide resin film.
JP23610492A 1992-09-03 1992-09-03 Semiconductor device Pending JPH0684886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23610492A JPH0684886A (en) 1992-09-03 1992-09-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23610492A JPH0684886A (en) 1992-09-03 1992-09-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0684886A true JPH0684886A (en) 1994-03-25

Family

ID=16995797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23610492A Pending JPH0684886A (en) 1992-09-03 1992-09-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0684886A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7741705B2 (en) 2006-08-29 2010-06-22 Oki Semiconductor Co., Ltd. Semiconductor device and method of producing the same
US10384176B2 (en) 2012-12-25 2019-08-20 Kajiwara Inc. Stirring device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7741705B2 (en) 2006-08-29 2010-06-22 Oki Semiconductor Co., Ltd. Semiconductor device and method of producing the same
US10384176B2 (en) 2012-12-25 2019-08-20 Kajiwara Inc. Stirring device

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