JPS6321341B2 - - Google Patents
Info
- Publication number
- JPS6321341B2 JPS6321341B2 JP53007279A JP727978A JPS6321341B2 JP S6321341 B2 JPS6321341 B2 JP S6321341B2 JP 53007279 A JP53007279 A JP 53007279A JP 727978 A JP727978 A JP 727978A JP S6321341 B2 JPS6321341 B2 JP S6321341B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- mos
- diffusion layer
- dummy
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000002161 passivation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000011109 contamination Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
この発明はMOSLSI等のMOS半導体装置にお
けるダミーMOS素子に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dummy MOS element in a MOS semiconductor device such as MOSLSI.
MOSLSIにおいて、MOS素子のVth（しきい値）
を知るために同じ半導体基板上に形成したその
MOS素子と同一構造のダミーMOS素子を使用す
ることが知られている。従来のダミーMOS素子
は第１図に示すように例えばｐ型シリコン基板１
上にフイルド酸化膜２により囲まれたゲート酸化
膜３を形成し、この上にポリシリコンゲート４を
形成するがこのゲートは基板とは電気的に絶縁し
ていた。さらに上記ゲートの上をパシベイシヨン
膜５で保護し、ゲートの一部にアルミニウム電極
６を接続していた。上記パシベイシヨン膜として
耐湿性が大で、基板表面の段差をカバレージし、
しかもクラツクの入りにくいプラズマナイトライ
ド膜（Ｐ−Si3N4）が多く使われるが、プラズマ
放電中でデポジシヨンするとき電子の一部がダミ
ーMOS素子の一つにチヤージアツプし、いわゆ
るBT（バイアス・テンパラチヤ）処理効果が生
じVthが変動する。すなわち、バイアスをかける
と（＋）の場合電子がシリコン・SiO2界面に移
動しVthが小さくなり、（−）の場合は上方へ移動
してVthが大きくなる。なお、400―500℃、10―
60分で熱処理を施せばBT効果はなくなるがポリ
シリコンの高抵抗性が低くなる。LSIの回路を構
成するMOSのゲートは必ず拡散層を通して基板
に接続しているので、このような問題はなく、従
つて従来のダミーMOSでは回路内部のMOSの
Vthを推定できなくなるという欠点があつた。 In MOSLSI, the V th (threshold value) of the MOS element
In order to understand the
It is known to use a dummy MOS element having the same structure as the MOS element. A conventional dummy MOS element is made of, for example, a p-type silicon substrate 1 as shown in FIG.
A gate oxide film 3 surrounded by a field oxide film 2 is formed thereon, and a polysilicon gate 4 is formed thereon, but this gate is electrically insulated from the substrate. Further, the top of the gate was protected with a passivation film 5, and an aluminum electrode 6 was connected to a part of the gate. As the passivation film mentioned above, it has high moisture resistance and covers steps on the substrate surface.
Moreover, plasma nitride film (P-Si 3 N 4 ), which is difficult to crack, is often used, but when deposited in plasma discharge, some of the electrons are charged up to one of the dummy MOS elements, resulting in so-called BT (bias film). (temperature) processing effect occurs and V th fluctuates. That is, when a bias is applied, in the case of (+) electrons move to the silicon/SiO 2 interface and V th decreases, and in the case of (-) they move upward and V th increases. In addition, 400-500℃, 10-
If heat treatment is performed for 60 minutes, the BT effect will disappear, but the high resistance of polysilicon will decrease. Since the gate of the MOS that makes up an LSI circuit is always connected to the substrate through a diffusion layer, there is no problem like this, and therefore with conventional dummy MOS, the MOS inside the circuit is
The drawback was that V th could not be estimated.
この発明は上記した従来技術の欠点を取除くべ
くなされたものであり、その目的はMOSLSIに
おけるMOS素子のVthを正確に知ることで不良解
析を容易ならしめることにある。 The present invention was made to eliminate the above-mentioned drawbacks of the prior art, and its purpose is to facilitate failure analysis by accurately knowing the V th of a MOS element in MOSLSI.
上記目的を達成するため、この発明はダミー
MOS素子において、半導体基板の一部に拡散層
によるpn接合を形成し、この拡散層にゲートを
接続すること、すなわち、MOS半導体基板上に
ゲート絶縁膜が形成され、前記ゲート絶縁膜上に
ゲート及びプラズマナイトライド膜が形成された
ダミーMOS半導体素子を有する半導体装置にお
いて、前記MOS半導体基板内に前記MOS半導体
基板と異なる導電型の拡散層が形成され、前記ゲ
ートと前記拡散層との間を導電性配線手段により
接続したダミーMOS半導体素子を有することを
特徴とする半導体装置を要旨とする。 In order to achieve the above purpose, this invention
In a MOS device, a pn junction is formed by a diffusion layer in a part of a semiconductor substrate, and a gate is connected to this diffusion layer. In other words, a gate insulating film is formed on the MOS semiconductor substrate, and a gate is connected to the gate insulating film on the MOS semiconductor substrate. and a semiconductor device having a dummy MOS semiconductor element on which a plasma nitride film is formed, wherein a diffusion layer of a conductivity type different from that of the MOS semiconductor substrate is formed in the MOS semiconductor substrate, and a diffusion layer is formed between the gate and the diffusion layer. The gist of the present invention is a semiconductor device characterized by having dummy MOS semiconductor elements connected by conductive wiring means.
以下実施例にそつて本発明を説明する。 The present invention will be explained below with reference to Examples.
第２図は本発明によるダミーMOS素子の原理
的構造を示すもので、第１図で示した従来例のも
のとの共通構成部分は同一指示番号で示す。すな
わち、ｐ型シリコン基板１の一部にn+型拡散層
７を形成し、ダミーMOS素子のゲートのアルミ
ニウム電極をこの拡散層７にオーミツク接続す
る。このような構造において、プラズマ・ナイト
ライド膜５のデポジシヨン時にゲートにとびこむ
電子は拡散層（クランプダイオードとなる）を介
して基板に流れることにより前記したようなBT
効果はおこらず、したがつてダミーMOS素子の
Vthは変動することがなく、前記発明の目的が達
成できる。 FIG. 2 shows the basic structure of a dummy MOS device according to the present invention, and common components with the conventional example shown in FIG. 1 are designated by the same reference numbers. That is, an n + type diffusion layer 7 is formed in a part of the p-type silicon substrate 1, and the aluminum electrode of the gate of the dummy MOS element is ohmicly connected to this diffusion layer 7. In such a structure, the electrons that fly into the gate during the deposition of the plasma nitride film 5 flow to the substrate via the diffusion layer (which becomes a clamp diode), resulting in the formation of the BT as described above.
No effect occurs, so the dummy MOS element
V th does not vary, and the object of the invention can be achieved.
現在、メモリ、MC関係の半導体製品において
生産性のよいプラスチツクパツケージ化のためパ
シベイシヨン膜としてプラズマナイトライド膜を
使用しており、これらの製品の総てに本発明は適
用できる。この発明により、ダミーMOSを使用
したPQC管理や、Vth、耐圧、汚染による不良の
解析が完全に行えるようになつた。 Currently, plasma nitride films are used as passivation films in memory and MC-related semiconductor products to produce plastic packages with high productivity, and the present invention can be applied to all of these products. This invention has made it possible to completely perform PQC management using dummy MOS and analysis of defects due to V th , withstand voltage, and contamination.
本発明は前記実施例に限定されず、これ以外に
下記のような種々の変形例を有する。 The present invention is not limited to the above-mentioned embodiments, but has various modifications as described below.
ダミーMOS素子の構造において、クランプダ
イオード（n+型拡散層）７に接続するアルミニ
ウム配線６の幅を細く規定する。すなわち第３図
ａに示すように、ゲートをクランプした場合、ゲ
ートを（−）にするとpn接合が順方向となり、
（−）電位が印加できないため不良解析などに不
都合である。そこでアルミニウムの幅を細くする
ことにより、大きい電流で熔断させるが、同図ｂ
に示すようにパシベイシヨン膜に穴８をあけてお
き、必要によりプローブ等により切断できるよう
にする。 In the structure of the dummy MOS element, the width of the aluminum wiring 6 connected to the clamp diode (n + type diffusion layer) 7 is defined to be narrow. In other words, as shown in Figure 3a, when the gate is clamped, when the gate is set to (-), the pn junction becomes forward direction.
(-) This is inconvenient for failure analysis because a potential cannot be applied. Therefore, by making the width of the aluminum thinner, it is possible to melt it with a larger current.
As shown in Figure 2, a hole 8 is made in the passivation membrane so that it can be cut with a probe or the like if necessary.
第４図に示すようにクランプダイオードへの接
続にアルミニウムを用いないでポリシリコン９を
用いる。前記第３図の構造ではアルミニウムを熔
断した際に、アルミニウムが周囲に飛び散り汚染
の原因となる可能性がある。又、ポリシリコンは
アルミニウムに比して抵抗が大きいため、同じ電
流で熔断する場合熱発生が大きく熔断し易いとい
う利点がある。 As shown in FIG. 4, polysilicon 9 is used instead of aluminum for connection to the clamp diode. In the structure shown in FIG. 3, when aluminum is melted, the aluminum may scatter to the surrounding area and cause contamination. Furthermore, since polysilicon has a higher resistance than aluminum, it has the advantage that it generates more heat and is easier to melt when melted with the same current.
第１図は従来のダミーMOS素子の例を示す断
面図、同図ａはその等価回路図である。第２図は
本発明によるダミー素子の実施例を示す断面図、
同図ａはその等価回路図である。第３図ａは本発
明の他の実施例を示す平面図、同図ｂはその一部
断面図、第４図は本発明のさらに他の実施例を示
す平面図である。
１…ｐ型シリコン基板、２…フイルド酸化膜、
３…ゲート酸化膜、４…ゲートポリシリコン層、
５…パシベイシヨン膜、６…アルミニウム電極、
７…拡散層（クランプダイオード）、８…穴、９
…ポリシリコン電極。
FIG. 1 is a sectional view showing an example of a conventional dummy MOS element, and FIG. 1A is its equivalent circuit diagram. FIG. 2 is a sectional view showing an embodiment of a dummy element according to the present invention;
Figure a is its equivalent circuit diagram. FIG. 3a is a plan view showing another embodiment of the present invention, FIG. 3b is a partially sectional view thereof, and FIG. 4 is a plan view showing still another embodiment of the present invention. 1...p-type silicon substrate, 2...field oxide film,
3... Gate oxide film, 4... Gate polysilicon layer,
5... Passivation film, 6... Aluminum electrode,
7... Diffusion layer (clamp diode), 8... Hole, 9
...Polysilicon electrode.
Claims (1)
れ、前記ゲート絶縁膜上にゲート及びプラズマナ
イトライド膜が形成されたダミーMOS半導体素
子を有する半導体装置において、前記MOS半導
体基板内に前記MOS半導体基板と異なる導電型
の拡散層が形成され、前記ゲートと前記拡散層と
の間を導電性配線手段により接続したダミー
MOS半導体素子を有することを特徴とする半導
体装置。 ２ 前記導電性配線手段の少なくとも一部はアル
ミニウム配線又はポリシリコン配線であることを
特徴とする特許請求の範囲第１項記載の半導体装
置。[Scope of Claims] 1. A semiconductor device having a dummy MOS semiconductor element in which a gate insulating film is formed on a MOS semiconductor substrate, and a gate and a plasma nitride film are formed on the gate insulating film, wherein A dummy in which a diffusion layer of a conductivity type different from that of the MOS semiconductor substrate is formed, and the gate and the diffusion layer are connected by conductive wiring means.
A semiconductor device characterized by having a MOS semiconductor element. 2. The semiconductor device according to claim 1, wherein at least a part of the conductive wiring means is an aluminum wiring or a polysilicon wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP727978A JPS54101294A (en) | 1978-01-27 | 1978-01-27 | Dummy mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP727978A JPS54101294A (en) | 1978-01-27 | 1978-01-27 | Dummy mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54101294A JPS54101294A (en) | 1979-08-09 |
| JPS6321341B2 true JPS6321341B2 (en) | 1988-05-06 |
Family
ID=11661580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP727978A Granted JPS54101294A (en) | 1978-01-27 | 1978-01-27 | Dummy mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54101294A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141025U (en) * | 1989-04-25 | 1990-11-27 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60177640A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH05275692A (en) * | 1992-03-25 | 1993-10-22 | Sony Corp | Semiconductor device and manufacture thereof |
| JP2006024601A (en) * | 2004-07-06 | 2006-01-26 | Seiko Instruments Inc | Field effect mos transistor |
-
1978
- 1978-01-27 JP JP727978A patent/JPS54101294A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141025U (en) * | 1989-04-25 | 1990-11-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54101294A (en) | 1979-08-09 |
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