JPS6214944B2 - - Google Patents
Info
- Publication number
- JPS6214944B2 JPS6214944B2 JP52106673A JP10667377A JPS6214944B2 JP S6214944 B2 JPS6214944 B2 JP S6214944B2 JP 52106673 A JP52106673 A JP 52106673A JP 10667377 A JP10667377 A JP 10667377A JP S6214944 B2 JPS6214944 B2 JP S6214944B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- heat
- layer
- thermal conductivity
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本願は発生した熱を効率良く放散し得る半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present application relates to a semiconductor device that can efficiently dissipate generated heat.
従来一半導体基板上に複数の回路素子を形成し
た集積回路装置において発生した熱は回路が形成
されている半導体基板と回路素子を保護している
SiO2等の絶縁物質とを介して伝導する。このう
ち絶縁物質に伝導された熱は集積回路を保護して
いるリンガラス(PSG)及びこれに含まれるN2
ガス等を介してパツケージ材であるエポキシ樹脂
等に伝導される。そして、このエポキシ樹脂より
外部へ熱放散される。又、基板への熱は基板が装
着される熱伝導率の高い金属導電板等が放熱板と
しても働く為にこれによつて外部へ放散される。
集積回路を形成する際に基板としてはSiが一般に
用いられる。この熱伝導率は約0.84J/cmsecであ
り、SiO2の熱伝導率は約1.9×10-3J/cmsecで、
PSG及びエポキシ樹脂の熱伝導率もほぼSiO2と同
じオーダーである。又、N2ガスの熱伝導率は約
5.4×10-4J/cmsecである。これからわかる様に
SiO2、PSG、エポキシ樹脂、及びN2ガスの熱伝
導率はSiの熱伝導率に比較して非常に低い。この
為、熱伝導の効率が悪く回路を構成している金属
配線等は発熱源の温度とほぼ同じ程度に保たれた
ままとなり、次第に温度が上昇する。それによ
り、素子の劣化、特性の変動などが起こる可能性
がある。 Conventionally, heat generated in integrated circuit devices in which multiple circuit elements are formed on one semiconductor substrate protects the semiconductor substrate on which the circuit is formed and the circuit elements.
Conducts through insulating materials such as SiO 2 . Of this, the heat conducted to the insulating material is absorbed by the phosphor glass (PSG) that protects the integrated circuit and the N2 contained in it.
It is conducted to the package material such as epoxy resin through gas etc. Heat is then dissipated to the outside from this epoxy resin. Furthermore, the heat to the substrate is dissipated to the outside by a metal conductive plate or the like with high thermal conductivity on which the substrate is attached, which also acts as a heat sink.
Si is commonly used as a substrate when forming integrated circuits. This thermal conductivity is approximately 0.84 J/cmsec, and the thermal conductivity of SiO 2 is approximately 1.9×10 -3 J/cmsec,
The thermal conductivity of PSG and epoxy resin is also approximately on the same order as SiO 2 . Also, the thermal conductivity of N2 gas is approximately
It is 5.4×10 -4 J/cmsec. As you will see
The thermal conductivity of SiO 2 , PSG, epoxy resin, and N 2 gas is very low compared to that of Si. For this reason, the metal wiring and the like that constitute the circuit, which have poor heat conduction efficiency, remain at approximately the same temperature as the heat source, and the temperature gradually rises. This may cause deterioration of the element, variation in characteristics, etc.
本願は上記の様な欠点を解消し、効率良く熱を
放散することができる半導体装置を提供すること
を目的とする。 It is an object of the present application to provide a semiconductor device that can eliminate the above-mentioned drawbacks and efficiently dissipate heat.
本願の他の目的は、回路素子を保護している
SiO2等の絶縁物のほぼ全面に金属などの高い熱
伝導率を有する物質を被覆し、この物質により絶
縁物を介して伝導されてきた熱を吸収し、その熱
を基板との接触部を介して基板に伝導することに
より効率良く熱を放散した半導体装置を提供する
ことを目的とする。 Another purpose of the present application is to protect circuit elements.
Almost the entire surface of an insulator such as SiO 2 is coated with a substance with high thermal conductivity such as a metal, and this material absorbs the heat conducted through the insulator and transfers that heat to the contact area with the substrate. An object of the present invention is to provide a semiconductor device in which heat is efficiently dissipated by conduction to a substrate through the heat exchanger.
本願を図面にもとずいて説明する。 The present application will be explained based on the drawings.
第1図にはSi基板に形成されたMOS形トラン
ジスタを示している。これは、Si基板1にSiO2か
ら成るフイールド酸化膜2を形成した後この酸化
膜2の一部を除去し、その部分にSiO2から成る
ゲート酸化膜3及びゲート電極となる多結晶Si層
4を形成する。そしてこのゲート酸化膜3及び多
結晶Si層4の一部を除去し、この部分からボロン
等の不純物を基板1に拡散しソース5及びドレイ
ン6とする。後SiO2等の絶縁膜7によりゲート
電極を絶縁し、それからソース電極8及びドレイ
ン電極9をAl等で形成する。集積回路装置にお
いてはこの様なトランジスタが複数形成される。 FIG. 1 shows a MOS transistor formed on a Si substrate. After forming a field oxide film 2 made of SiO 2 on a Si substrate 1, a part of this oxide film 2 is removed, and a gate oxide film 3 made of SiO 2 and a polycrystalline Si layer that will become the gate electrode are deposited on that part. form 4. A portion of this gate oxide film 3 and polycrystalline Si layer 4 is removed, and impurities such as boron are diffused into the substrate 1 from this portion to form a source 5 and a drain 6. Afterwards, the gate electrode is insulated with an insulating film 7 made of SiO 2 or the like, and then a source electrode 8 and a drain electrode 9 are formed of Al or the like. A plurality of such transistors are formed in an integrated circuit device.
その後第2図に示す様にSiO2から成る絶縁層
10を全面に形成する。 Thereafter, as shown in FIG. 2, an insulating layer 10 made of SiO 2 is formed over the entire surface.
つぎに第3図に示す様に回路素子が形成されな
い部分のSiO2層を除去し、コンタクトホール1
1を形成する。このコンタクトホール11の面積
は大きい方が好ましい。というのは、後の工程で
形成される金属層に伝導された熱を効率良く基板
1に伝導する為には、金属層と基板1との接触面
積が大きい程熱伝導の効率が良いからである。 Next, as shown in Figure 3, the SiO 2 layer is removed from the part where the circuit element is not formed, and the contact hole 1
Form 1. It is preferable that the area of this contact hole 11 be large. This is because, in order to efficiently conduct the heat conducted to the metal layer formed in a later process to the substrate 1, the larger the contact area between the metal layer and the substrate 1, the better the efficiency of heat conduction. be.
つぎに第4図に示す様にコンタクトホール11
及び絶縁層10上の全面にAl層12を被覆す
る。このAl層12はボンデイングパツド上及び
スクライブ部分には被覆されない。これはボンデ
イングパツドは外部端子との接続リードが接続さ
れる為であり、スクライブ部分は、薄い方が楽に
スクライブできる為である。又、Alの熱伝導率
は約2.3J/cmsecであり、SiO2などより非常に大
きい。 Next, as shown in FIG.
Then, the entire surface of the insulating layer 10 is covered with an Al layer 12. This Al layer 12 does not cover the bonding pad or the scribe area. This is because the bonding pad is connected to the connection lead to the external terminal, and the thinner the scribe portion is, the easier it is to scribe. Furthermore, the thermal conductivity of Al is approximately 2.3 J/cmsec, which is much higher than that of SiO 2 and the like.
この様に形成された回路はPSGなどの保護膜に
より保護される。そして、基板1は金属導電板等
にハンダ付けされ、外部リードとの間がリード線
で接続される。後エポキシ等の樹脂でモールドさ
れる。この金属導電板は放熱板としても効果があ
る。 The circuit formed in this way is protected by a protective film such as PSG. Then, the substrate 1 is soldered to a metal conductive plate or the like, and connected to external leads using lead wires. It is then molded with resin such as epoxy. This metal conductive plate is also effective as a heat sink.
以上の様に集積回路を形成すれば、その動作時
の発生熱は基板及び放熱板を通して効率良く外部
へ放散できる。 By forming an integrated circuit as described above, the heat generated during its operation can be efficiently dissipated to the outside through the substrate and the heat sink.
以下これについて説明する。 This will be explained below.
まずトランジスタなどで発生した熱の一部は基
板1に直接伝導する。そして他の熱はゲート電極
保護膜7及び絶縁層10に伝導し、更にこの熱は
Al層12に伝導する。Al層12に伝導した熱の
ほとんどは基板1との接触部を通して基板1へ伝
導する。これは、Al層12上に形成されるPSG
のパツシベーシヨン層及びその上のモールド用エ
ポキシ樹脂の熱伝導率よりSiの熱伝導率の方が高
い為である。 First, a portion of the heat generated by the transistor etc. is directly conducted to the substrate 1. Then, other heat is conducted to the gate electrode protective film 7 and the insulating layer 10, and this heat is further
conducts to the Al layer 12. Most of the heat conducted to the Al layer 12 is conducted to the substrate 1 through the contact portion with the substrate 1. This is the PSG formed on the Al layer 12.
This is because the thermal conductivity of Si is higher than that of the passivation layer and the epoxy resin for the mold on it.
この様に発生した熱のほとんどが基板1に伝導
する。この為、基板1が装着される放熱板として
も効果のある金属導電板を介して発生熱を効率良
く外部へ放散させ得る。それにより温度上昇をお
さえることができ回路の熱劣化及び特性変動を防
止でき、回路の信頼性を向上させることができ
る。 Most of the heat generated in this way is conducted to the substrate 1. Therefore, the generated heat can be efficiently dissipated to the outside through the metal conductive plate, which is also effective as a heat sink to which the substrate 1 is mounted. Thereby, temperature rise can be suppressed, thermal deterioration and characteristic fluctuations of the circuit can be prevented, and reliability of the circuit can be improved.
又、Alは全面に被覆しているので、外部の雑
音から回路を保護するシールド材としての効果も
ある。 Furthermore, since the entire surface is coated with Al, it also functions as a shielding material that protects the circuit from external noise.
尚実施例においてはAlを用いたが、これは、
他の熱伝導率の高い物質でも良いことは当然であ
る。又、Alを直接基板に接触させる必要はな
く、熱が良好に基板に伝導する様な中間層が介在
しても良い。 In addition, Al was used in the example, but this
It goes without saying that other materials with high thermal conductivity may also be used. Further, it is not necessary to bring Al into direct contact with the substrate, and an intermediate layer that can conduct heat well to the substrate may be interposed.
第1図乃至第4図は本願の一実施例を説明する
為の各工程における半導体装置の断面図である。
1……基板、10……パツシベーシヨン層、1
1……コンタクトホール、12……Al層。
1 to 4 are cross-sectional views of a semiconductor device at each step for explaining an embodiment of the present application. 1... Substrate, 10... Passivation layer, 1
1...Contact hole, 12...Al layer.
Claims (1)
子が形成された部分及び回路素子の形成されない
部分を有する半導体基板と、 前記回路素子を被覆する絶縁膜と、 この絶縁膜上に形成された熱伝導層と、 この熱伝導層上に形成された保護膜と、 前記回路素子が形成されない部分の前記半導体
基板と前記熱伝導層とを、前記絶縁膜及び前記保
護膜よりも熱伝導率の高い材質を用いて熱的に接
続した事を特徴とする半導体装置。[Scope of Claims] 1. A lead frame, a semiconductor substrate placed on the lead frame and having a portion where a circuit element is formed and a portion where no circuit element is formed, an insulating film covering the circuit element. , a thermally conductive layer formed on this insulating film, a protective film formed on this thermally conductive layer, and a portion of the semiconductor substrate and the thermally conductive layer in which the circuit element is not formed to be connected to the insulating film and the thermally conductive layer. A semiconductor device characterized in that the semiconductor device is thermally connected using a material having higher thermal conductivity than the protective film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10667377A JPS5440583A (en) | 1977-09-07 | 1977-09-07 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10667377A JPS5440583A (en) | 1977-09-07 | 1977-09-07 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5440583A JPS5440583A (en) | 1979-03-30 |
JPS6214944B2 true JPS6214944B2 (en) | 1987-04-04 |
Family
ID=14439581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10667377A Granted JPS5440583A (en) | 1977-09-07 | 1977-09-07 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5440583A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01214048A (en) * | 1988-02-23 | 1989-08-28 | Fujitsu Ltd | Semiconductor integrated device |
US6331722B1 (en) | 1997-01-18 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Hybrid circuit and electronic device using same |
DE112009005017T5 (en) * | 2009-06-29 | 2012-07-26 | Fujitsu Limited | Semiconductor device and method for manufacturing a semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5080787A (en) * | 1973-11-14 | 1975-07-01 | ||
JPS5147371A (en) * | 1974-10-21 | 1976-04-22 | Fujitsu Ltd | HANDOTA ISOCHI |
-
1977
- 1977-09-07 JP JP10667377A patent/JPS5440583A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5080787A (en) * | 1973-11-14 | 1975-07-01 | ||
JPS5147371A (en) * | 1974-10-21 | 1976-04-22 | Fujitsu Ltd | HANDOTA ISOCHI |
Also Published As
Publication number | Publication date |
---|---|
JPS5440583A (en) | 1979-03-30 |
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