JPS58116828A - クロツクパルス発生回路 - Google Patents

クロツクパルス発生回路

Info

Publication number
JPS58116828A
JPS58116828A JP56210394A JP21039481A JPS58116828A JP S58116828 A JPS58116828 A JP S58116828A JP 56210394 A JP56210394 A JP 56210394A JP 21039481 A JP21039481 A JP 21039481A JP S58116828 A JPS58116828 A JP S58116828A
Authority
JP
Japan
Prior art keywords
phase
output
circuit
signal
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56210394A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6362144B2 (enrdf_load_stackoverflow
Inventor
Tetsuo Inose
猪瀬 哲男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56210394A priority Critical patent/JPS58116828A/ja
Publication of JPS58116828A publication Critical patent/JPS58116828A/ja
Publication of JPS6362144B2 publication Critical patent/JPS6362144B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56210394A 1981-12-30 1981-12-30 クロツクパルス発生回路 Granted JPS58116828A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56210394A JPS58116828A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56210394A JPS58116828A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Publications (2)

Publication Number Publication Date
JPS58116828A true JPS58116828A (ja) 1983-07-12
JPS6362144B2 JPS6362144B2 (enrdf_load_stackoverflow) 1988-12-01

Family

ID=16588596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56210394A Granted JPS58116828A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Country Status (1)

Country Link
JP (1) JPS58116828A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02211735A (ja) * 1989-02-10 1990-08-23 Matsushita Electric Ind Co Ltd ビット同期装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02211735A (ja) * 1989-02-10 1990-08-23 Matsushita Electric Ind Co Ltd ビット同期装置

Also Published As

Publication number Publication date
JPS6362144B2 (enrdf_load_stackoverflow) 1988-12-01

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