JPS5810839A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5810839A JPS5810839A JP56111177A JP11117781A JPS5810839A JP S5810839 A JPS5810839 A JP S5810839A JP 56111177 A JP56111177 A JP 56111177A JP 11117781 A JP11117781 A JP 11117781A JP S5810839 A JPS5810839 A JP S5810839A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- frame
- integrated circuit
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
この発明は集積回路素子の集積度を向上することができ
る半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that can improve the degree of integration of integrated circuit elements.
従来の半導体装置は１テツグ１パツケージカ主流である
。すなわち、第１ｒ！！ＪＫ示すように、フレームα）
上にチック（２）１ｉ−取ル付けたのち、フレーム（１
）のリード（１ａ）とテップ（２）の電極とをワイヤｅ
）により、電気的に接続する。そして、チップ（２）を
保護するため、モールド樹脂（４）により一体に成形す
るものである。In conventional semiconductor devices, one test and one package are mainstream. That is, the 1st r! ! Frame α) as shown in JK
After attaching the tick (2) 1i- to the top, attach the frame (1
) and the electrode of the tip (2) with wire e.
) to make an electrical connection. In order to protect the chip (2), it is integrally molded with mold resin (4).
しかしながら、従来の半導体装置は１テツプ１パツケー
ジのため、スペースファクタが悪く、シかも機能上から
も有効でないなどの欠点があった。However, since the conventional semiconductor device has one step and one package, it has disadvantages such as a poor space factor, and is not effective in terms of space and function.
しｆｃがって、この発明の目的は複数個の同一テツクあ
るいは異種チップを１パツケージに実装することによ〕
、スペースファクタがよく、シかも機能も大幅に向上す
る半導体装置を提供するものである。Therefore, the object of the present invention is to package a plurality of chips of the same technology or different types into one package.
The present invention provides a semiconductor device with a good space factor and greatly improved functionality.
このような目的を達成するため、この発明は集積回路を
形成した第１のテクノと、この第１のチップに形成し念
集積回路とミラー反転の関係あるいは補間関係になるよ
うに集積回路を形成した第２のチップとが互に対向する
ように配置し、モールドあるいはセラミックパッケージ
で組立て、一体化構造にするものであり、以下実権例を
用いて詳細に説明する。In order to achieve such an object, the present invention includes a first technology that forms an integrated circuit, a virtual integrated circuit that is formed on this first chip, and an integrated circuit that is formed in a mirror-inversion or interpolation relationship. The two chips are placed so as to face each other and assembled using a mold or a ceramic package to form an integrated structure, which will be explained in detail below using a practical example.
第２図はこの発明に係る半導体装置の一実總例を示す断
面図である。同図において、（５）は前記テップ（２）
Ｋ形成した集積回路とミラー反転の関係あるいは補間関
係にある集積回路を形成する第２チツク、（６）Ｆｉこ
の１１２チツク（５）の電極とフレーム（１）のリード
（１ｍ）とを電気的に継ぐワイヤである。FIG. 2 is a sectional view showing an actual example of a semiconductor device according to the present invention. In the same figure, (5) is the step (2)
A second chip (6) that forms an integrated circuit in a mirror-inversion or interpolation relationship with the integrated circuit formed by K, electrically connects the electrode of this 112 chip (5) and the lead (1 m) of the frame (1). This is the wire that connects to.
この構成による半導体装置においてはチップ（２）と第
２チツプ（５）とはミラー反転の関係あるいは補間関係
にあるため、フレーム（１）をはさんで、一方の面にテ
クノ（２）￥ｒ取付け、他方の面に第２チツク（５）を
取り付けることにより、各チップ（２）および（５）上
に設けた電極のうち、相互に共通な電極は対向する。そ
して、チップ（２）および価）の電極とフレーム（１）
のリード（１ａ）とをワイヤ（３）および（６）Ｋより
容易に接続することができる。例えば第３図に示すよう
に、チップ（２）と第２チツプ（５）の共通な電極をリ
ード（１ｍ−３） 、 （１ｍ−４）および（１ａ→）
、（ｔａ−７）に接続する。そして、チップ（２）の独
立に必要な電極は実線で示すように、ワイヤによ）リー
ド（１＠−１）および（１ｍ−５）に接続し、ｆ”ｊ／
プＧ）ノ独立に必要な電極は点線で示すように、ワイヤ
によりリード（１ｍ−２）および（１ｍ−６）に接続す
る。そして、モールドあるいはセラミックパッケージで
組立て、一体化構造にするものである。In the semiconductor device with this configuration, the chip (2) and the second chip (5) are in a mirror inversion relationship or an interpolation relationship, so the technograph (2) is placed on one side with the frame (1) in between. By attaching the second chip (5) to the other surface, common electrodes among the electrodes provided on each chip (2) and (5) face each other. and the electrodes of the chip (2) and the valence) and the frame (1)
can be more easily connected to the lead (1a) than the wires (3) and (6)K. For example, as shown in Figure 3, the common electrodes of chip (2) and second chip (5) are connected to leads (1m-3), (1m-4) and (1a→)
, (ta-7). Then, the independently necessary electrodes of the chip (2) are connected to the leads (1@-1) and (1m-5) by wires, as shown by the solid lines, and f''j/
The independently necessary electrodes of step G) are connected to leads (1m-2) and (1m-6) by wires, as shown by dotted lines. Then, it is assembled using a mold or a ceramic package to form an integrated structure.
繭４図はこの発明鈍係る半導体装置の他の実論例を示す
断面側面図である。この実施例ではテクノ＠）ｊ？よび
＠２テップ（５）に突起電極（７）を設け、フレーム（
１）のり−ド０１）に固着することによシ、電気的な接
続とチックの固着管同時に行なう。そして、チップＣ）
と嬉２テッグφ）と０間に高純度樹脂−）を充填したの
ち、通常のモールド樹脂１）Ｋよ）パッシベーションす
る。このように構成することにより、例えば記憶素子な
どの対α線対策を必要とする場合ＫＩ！＃に有効である
。そして、嬉５図に示すようｋ、共通電＠（ムｓ）、（
Ａｓ）−（ムｓ）、（４）はそれぞれ独立的に配置し、
突起電極とするが、分離を必要とする電＠（ムり、（ム
茸）、（ム■）、（ム１１）では素子上で電＠（ム鳳）
と（ム雪）、（ム■）と（ム１雪）１＊続し、テクノα
）では電＠（ム１）および（ム１１）に奥起電＠を設け
、チックの）では電＠（ム雪）および（ムｔｓ）Ｋ＊ｌ
ｌ電＠を設け、フレームα）の対応するリード（１ｍ−
１） ＝ （ｉｍ−１２）に接続する。なお、実線はテ
ッグシ）の電１とフレームａ）のリードとｔｍぐワイヤ
を示し、点線＊ＩＩ２テッグ優）の電ｌＩｉトフレーム
α）のリードとを継ぐワイヤを示す。Figure 4 is a sectional side view showing another practical example of a semiconductor device according to the present invention. In this example, techno@)j? Protruding electrodes (7) are provided on the and @2 steps (5), and the frame (
1) By fixing it to the glue board 01), electrical connection and tick fixing tube can be made at the same time. And chip C)
After filling the space between φ) and 0 with high-purity resin-), passivation is performed using normal mold resin 1)K. With this configuration, KI! Valid for #. Then, as shown in Figure 5, k, common electric @ (mus), (
As)-(Mus), (4) are each arranged independently,
Protruding electrodes are used, but in cases where separation is required (Mutake), (Mu■), and (Mu11), electric @(Muho) is used on the element.
and (muyuki), (mu■) and (mu1yuki) 1 * continued, techno α
), den@(mu1) and (mu11) have back electromotive @, and tick's) has den@(muyuki) and (muts)K*l
Provide a lead @, and connect the corresponding lead (1m-) of frame α).
1) Connect to = (im-12). Note that the solid line indicates the wire that connects the lead of the frame a) to the lead of the frame a), and the dotted line indicates the wire that connects the lead of the frame α) of the frame α).
鎮６図はこの発明に係る半導体装置の更に他の実論例を
示す断面側面図である。同図において、Φ）嬬リード（
１０＠−１） −（１０ｍ−１２） （躯７１１参照
）およびこのリード（１０ｍ−１） 〜（１０ｍ−１２
）にそれぞれ接続する端子（１１）￥ｒ設けたセラミツ
クツくツケージ基板、（１２）は蓋である。なお、端子
（１１）はそｎぞれリード（１０ｍ−１）〜（１０ｍ−
１２）にメタライズなどにより接続されるが、第７図に
示すように、共通電極（ＡＩ） 、 （Ａｓ） 、 （
Ａｓ）および（ム１）＃ｉリード（１０ａ”３） 〜（
１０ｍ−６）に共通に接続され、独立的に必要な電極、
例えば（Ａｓ）はリード（１０ｍ−１）および（１０ａ
−２）に接続する。Figure 6 is a cross-sectional side view showing still another practical example of the semiconductor device according to the present invention. In the same figure, Φ) Tsumugi Reed (
10@-1) -(10m-12) (see body 711) and this lead (10m-1) ~(10m-12
), terminals (11) are provided on the ceramic shoe cage board, and (12) is the lid. In addition, each terminal (11) has a lead (10m-1) to (10m-1).
12) by metallization, etc., but as shown in Fig. 7, the common electrodes (AI), (As), (
As) and (Mu1) #i lead (10a”3) ~(
10m-6) commonly connected and independently required electrodes,
For example, (As) is lead (10m-1) and (10a
-2).
この実施例ではチップ（２）と第２チツプ（５）との間
の空間に特別な充填物ｔｍ織こさずとも、対α線は十分
で、理論的には必要はな−か、他の理由例えば誘電率の
向上などのために、シリコーン系樹脂などを充填しても
よく、その場合、素子の保饅膜としての効果が期待でき
る。In this embodiment, even without a special filling TM in the space between the chip (2) and the second chip (5), the amount of anti-α rays is sufficient, and theoretically there is no need for it. For example, in order to improve the dielectric constant, it may be filled with a silicone resin or the like, and in that case, it can be expected to be effective as a protective film for the element.
なお、以上の実施例では突起電極ｔｍ有する素子に替シ
、ビームリード素子、チーブアセ／ブリ素子を使用して
もよいことはもちろんである。また、突起電極は接合性
の点などを考慮して通常半田などを使用するが、接合後
の再溶融温度が高くなるように、フレームあるいはパッ
ケージの接合部のメタライズ紘選択するのが望ましく、
例えば鋼。In the above embodiments, it goes without saying that a beam lead element or a chip assembly/assembly element may be used instead of the element having the protruding electrode tm. In addition, solder is usually used for the protruding electrodes in consideration of bonding properties, but it is desirable to select metallized metal at the joints of the frame or package so that the remelting temperature after bonding is high.
For example, steel.
金、亜鉛あるｉ社鉛すンチの半田などをメッキなどの手
段により薄く所定の量だけ賦与することが必要である。It is necessary to apply a predetermined amount of gold, zinc, or the like solder using lead tints made by Company I in a thin layer by plating or other means.
以上詳細に説明したように、この発明に係る半導体装置
によればリード本数が２本程度増加するだけで、機能が
２倍になる。例えば１６リードの１６ Ｋ（ｔ））ＲＡ
Ｍ カ１８１Ｊ −）’０３２ Ｋ＠ＲムＭ となる。As described above in detail, according to the semiconductor device according to the present invention, the function can be doubled by increasing the number of leads by about two. For example, 16 K(t))RA with 16 leads
M Ka181J-)'032 K@RMM.
このように１実装密度を大幅に向上することができるな
どの効果がある。In this way, there are effects such as the ability to significantly improve the single packaging density.
第１図は従来の半導体装置を示す断面側面図、１１Ｅ２
図社この発明に係る半導体装置の一夷總例を示す断面側
面図、第３図ＨｇＩＺ図のチップの電極とフレームのリ
ードとの関係を示す平面図、縞４図はこの発明に係る半
導体装置の他の実施例を示す断面側面図、第５図Ｆｉ第
４図のチップの電極とフレームのリードとの関係を示す
平面図、第６図＃′ｉこの発明に係る半導体装置の更に
他の実施例を示す断面側面図、第７図は１１６図のチッ
プの電極とフレームのリードとの関係を示す平面図であ
る。
（１）−−−−フレーム、（１ｍ−１） 〜（１０，−
１２） ”・・リード、（２）・・・・チップ、（３）
−−−−ワイヤ、（４）・・・・モールド樹脂、（５
）・・・・第２チツク、（６）・・・・ワイヤ、（７）
・・・・突起電極、（８）・・・・、高純度樹脂、（９
）・・・・セラミックパッケージ基板、（１０ｍ−１）
〜（１０ａ−１２） ・・・・リード。
なお、図中、同一符号ｒｉ同一または相当部分を示す。
代理人 葛 野 信 −（外１名）
３．６
手続補正書（自発）
特許庁長官殿
１、事件の表示 特願昭 ６６−１１１１７７号
２、発明の名称
半導体装置
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号
名 称（６０１） 三菱電機株式会社代表者片山仁
八部
４、代理人
５、補正の対象
＋１１ 明細書の特許請求の範囲の欄（２１明細書の
発明の詳細な説明の欄
６、補正の内容
（１１明細書の「特許請求の範囲」を別紙のとおシ補正
する。
（２）同書第７頁第３行の「鉛すンチ」を「鉛リッチ」
と補正する。
以 上
別 紙
「（１１集積回路を形成した第１のチップと、この第１
のチップに形成した集積回路とミラー反転の開俵あるい
は補間関係に表るように集積回路を形成した館２のチッ
プとを互に対向するように配置し、モールドあるい紘セ
ラ之ツクパッケージで組立てて一体化構造にすることを
特徴とする半導体装置。
（２） 第１のチップを７レームの一方の面に固着し
、第２のチップをフレームの他方の面に固着することを
特徴とする特許請求の範囲第１項記載の半導体装置。
（３）各チップに突起電極を形成し、この突起電極を７
レームのリードに接続固定することを特徴とする特許請
求の範囲第１項記載の半導体装置。
（４）第１のチップと第２のチップとの間の空間に、α
線をしゃ断し且つ自ら発しない樹脂を充填することを特
徴とする特許請求の範囲第１項記載の半導体装５０
（５）前記突起電極のうち、所定の突起電極を２連に形
成し、この２連の突起電極のうち、第１のチップと第２
のチップでは互に異なる位置の突起電極をリードへの接
続に用いることを特徴とする特許請求の範囲第３項記載
の半導体装置。」以 上FIG. 1 is a cross-sectional side view showing a conventional semiconductor device, 11E2
Figure 3 is a cross-sectional side view showing a complete example of the semiconductor device according to the present invention, a plan view showing the relationship between the electrodes of the chip and the leads of the frame in Figure 3, and Figure 4 shows the semiconductor device according to the present invention. FIG. 5F is a plan view showing the relationship between the electrodes of the chip shown in FIG. 4 and the leads of the frame, FIG. FIG. 7 is a cross-sectional side view showing the embodiment, and a plan view showing the relationship between the electrodes of the chip and the leads of the frame shown in FIG. 116. (1)---Frame, (1m-1) ~(10,-
12) ”...Lead, (2)...Chip, (3)
-----Wire, (4)...Mold resin, (5
)...Second tick, (6)...Wire, (7)
...Protruding electrode, (8) ..., high purity resin, (9
)...Ceramic package substrate, (10m-1)
~(10a-12) ...Lead. In addition, in the drawings, the same reference numerals ri indicate the same or equivalent parts. Agent Shin Kuzuno - (1 other person) 3.6 Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Case description Patent Application No. 111177/1982 2, Name of invention semiconductor device 3, Person making amendment case Relationship with Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama Department 4, Agent 5 Subject of amendment + 11 Patent claims in the specification Scope column (detailed description of the invention column 6 in Specification 21, Contents of amendment (“Claims” in Specification 11 will be amended as a separate sheet. (2) Line 3 on page 7 of the same document) “Lead tint” is “lead rich”
and correct it. Attachment ``(11) The first chip forming the integrated circuit and this first chip
The integrated circuit formed on the chip of 1 and the chip of the building 2 on which the integrated circuit was formed are placed so as to face each other as shown in the open bag of mirror inversion or the interpolation relationship, and the integrated circuit is placed in a mold or in a Hiroceras package. A semiconductor device characterized by being assembled into an integrated structure. (2) The semiconductor device according to claim 1, wherein the first chip is fixed to one surface of the seven frames, and the second chip is fixed to the other surface of the frame. (3) Form a protruding electrode on each chip, and connect this protruding electrode to 7
2. The semiconductor device according to claim 1, wherein the semiconductor device is connected and fixed to a lead of a frame. (4) In the space between the first chip and the second chip, α
Semiconductor device 50 according to claim 1, characterized in that the semiconductor device 50 is filled with a resin that interrupts wires and does not emit itself. Of the two protruding electrodes, the first tip and the second tip
4. The semiconductor device according to claim 3, wherein protruding electrodes at different positions are used for connection to the leads in the chip. "that's all
Claims (1)
テップに形成した集積回路とミラー半輪の関係あるい鉱
補関関係になるように集積回路を形成し良第２０テッ１
とを互に対向するように配置し、モールドあるいはセラ
ミックパッケージで組立てて一体化構造にすることを特
徴とする半導体装置。 （２）ｌｉｔのチップをフレームの一方の面に固着し、
第２のテップｔフレームの他方の面Ｋ１１着すること管
特徴とする特許請求の範ｌｉ！８第１項記載の半導体装
置、 Ｃ）各チップに突起電極を形成し、この突起電極ｔフレ
ームのリードに接続固定することｔ−特徴とする特許請
求の範囲第１項記載の半導体装置。 （４）！ＩＩＩのテッグ七第２のチップとの間の空間に
、ａＩｉａをしゃ断し且つ自ら発しない樹脂を充填する
ことを特徴とする特許請求の範囲第１項記載の半導体素
子。 （５）前記突起電極のうち、１所定の突起電極を２連に
形成し、この２連の突起電極のうち、Ｉｌｌのチップと
第２のチックでは互に異なる位置の突起電極をリードへ
の接続に用いることを特徴とする特許請求の範囲第３項
記載の半導体装置。[Scope of Claims] (1) The integrated circuit is formed so that the first chip on which the integrated circuit is formed and the integrated circuit formed on this first step have a mirror half-ring relationship or complementary relationship. Shira 20th te 1
What is claimed is: 1. A semiconductor device characterized in that the semiconductor devices are arranged so as to face each other and assembled using a mold or a ceramic package to form an integrated structure. (2) Fix the lit chip to one side of the frame,
Claims characterized in that the second step t-frame is attached to the other surface K11. 8. The semiconductor device according to claim 1, characterized in that: C) a protruding electrode is formed on each chip, and the protruding electrode is connected and fixed to the lead of the frame. (4)! 2. The semiconductor device according to claim 1, wherein the space between the third chip and the second chip is filled with a resin that blocks aIia and does not emit itself. (5) Among the protruding electrodes, one predetermined protruding electrode is formed in two rows, and among these two series of protruding electrodes, the protruding electrodes at different positions for the Ill chip and the second tick are connected to the lead. 4. The semiconductor device according to claim 3, wherein the semiconductor device is used for connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111177A JPS5810839A (en) | 1981-07-14 | 1981-07-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111177A JPS5810839A (en) | 1981-07-14 | 1981-07-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5810839A true JPS5810839A (en) | 1983-01-21 |
| JPS628033B2 JPS628033B2 (en) | 1987-02-20 |
Family
ID=14554435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56111177A Granted JPS5810839A (en) | 1981-07-14 | 1981-07-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810839A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6028255A (en) * | 1983-07-26 | 1985-02-13 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPH0287661A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor storage device |
| WO1991014282A1 (en) * | 1990-03-15 | 1991-09-19 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| JPH05129517A (en) * | 1991-05-11 | 1993-05-25 | Goldstar Electron Co Ltd | Laminated type semiconductor package and manufacture thereof |
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008086489A2 (en) | 2007-01-10 | 2008-07-17 | Karamanos John C | Embedded heat exchanger for heating, ventilation, and air conditioning (hvac) systems and methods |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487173A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Semiconductor device |
| JPS5617050A (en) * | 1979-07-20 | 1981-02-18 | Nec Corp | Semiconductor device |
| JPS5624955A (en) * | 1979-08-07 | 1981-03-10 | Fujitsu Ltd | Semiconductor device |
| JPS5662351A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Semiconductor device for memory |
-
1981
- 1981-07-14 JP JP56111177A patent/JPS5810839A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487173A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Semiconductor device |
| JPS5617050A (en) * | 1979-07-20 | 1981-02-18 | Nec Corp | Semiconductor device |
| JPS5624955A (en) * | 1979-08-07 | 1981-03-10 | Fujitsu Ltd | Semiconductor device |
| JPS5662351A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Semiconductor device for memory |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6028255A (en) * | 1983-07-26 | 1985-02-13 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPH0287661A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor storage device |
| WO1991014282A1 (en) * | 1990-03-15 | 1991-09-19 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| JPH05129517A (en) * | 1991-05-11 | 1993-05-25 | Goldstar Electron Co Ltd | Laminated type semiconductor package and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS628033B2 (en) | 1987-02-20 |
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