JPS6025257A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6025257A JPS6025257A JP58134031A JP13403183A JPS6025257A JP S6025257 A JPS6025257 A JP S6025257A JP 58134031 A JP58134031 A JP 58134031A JP 13403183 A JP13403183 A JP 13403183A JP S6025257 A JPS6025257 A JP S6025257A
- Authority
- JP
- Japan
- Prior art keywords
- metallized layer
- lead
- metal piece
- chip
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置に係り導電性の金属片（ターミナル
チップ）を有する半導体装置の改良に閃する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device and is directed to improving a semiconductor device having a conductive metal piece (terminal chip).
ψ）技術の背景
半導体チップを収納する半導体パッケージには大別して
セラミックパッケージとプラスチックパッケージとがあ
りプラスチックパッケージの中では七ランク基板間にリ
ードフレームをはさみガラス封止する通常サーデツプ（
Ｃａｒｄｉｐ）と呼ばれているパッケージが、メタライ
ズ層を設けてメタル封止する多層セラミックパッケージ
に比べて安価に作成され、しかも信頼性が高いため一般
に広く用いられている。ψ) Technology Background Semiconductor packages that house semiconductor chips can be roughly divided into ceramic packages and plastic packages. Among plastic packages, there are usually cer-deep packages that sandwich a lead frame between seven-rank boards and seal them with glass.
A package called "Cardip" is generally widely used because it is cheaper to produce than a multilayer ceramic package in which a metallized layer is provided and sealed with metal, and it is highly reliable.
（Ｃ）従来技術と問題点
従来上記サーデツプ型パッケージに半導体チップが組立
てられた半導体装置について第１図に要部断面図（第２
図の■〜１′断面）、第２図にパッケージ基体の平面図
、第８図に導電性の金属片（ターミナルチップ）の拡大
断面図を示す。(C) Prior art and problems Regarding a conventional semiconductor device in which a semiconductor chip is assembled in the above-mentioned sur-deep package, FIG.
2 is a plan view of the package base, and FIG. 8 is an enlarged sectional view of a conductive metal piece (terminal chip).
第１図においてはパッケージ基体、２は該パッケージ基
体に形成されたメタライズ層、３は外部リード４を接着
してなるガラス材、５は半導体チップ、６は導電性の金
属片、７は金属細線、８はキャップ、９は接着封止用ガ
ラスを示す。In FIG. 1, the package base is shown, 2 is a metallized layer formed on the package base, 3 is a glass material to which external leads 4 are bonded, 5 is a semiconductor chip, 6 is a conductive metal piece, and 7 is a thin metal wire. , 8 indicates a cap, and 9 indicates an adhesive sealing glass.
図示したようにパッケージ基体１の中央四部の底面に設
けられたメタライズ層２上に半導体チクブイの背面がオ
ーミック接続になるように接続されている。As shown in the figure, the back surface of the semiconductor chip is connected to the metallized layer 2 provided on the bottom surface of the four central parts of the package base 1 so as to form an ohmic connection.
れている。It is.
所で一般にサーチツブパッケージのメタライズ層３は多
層セラミックパッケージと異なり／ぐツケーヅ基体１上
面に接着封止用ガラス８によって接着された外部リード
フレーム４と電気的に絶縁されているため半導体チップ
５の基板背面に導通が必要な場合にはメタライズ層２上
に第２図に示すように導電性部材よりなる金属片（ター
ミナルチップ）６を配設し、外部リードフレーム４の一
端子４Ａとの間に金線細線１０によってワイヤボンデン
グし電気的に接続せしめ該ターミナルチップ６を介して
半導体チップ５の基板に均油が行なわれている。尚半導
体チップ５上に形成されたワイヤボンデングバッド１１
はそれぞれ外部リードフレーム４にワイヤ７にて接続さ
れている。又−力半導体素子は高集積、高連化のため、
耐熱性において弱い設計となっており、出来るだけ低温
処理を行なうことが望ましい。そのため接着封止用ガラ
ス３・９は出来るだけ低い封着温度（約４００−４８０
℃）の部材で構成される場合がある。However, unlike a multilayer ceramic package, the metallized layer 3 of the search tube package is generally electrically insulated from the external lead frame 4 bonded to the top surface of the package base 1 by an adhesive sealing glass 8. If continuity is required on the back side of the board, a metal piece (terminal chip) 6 made of a conductive material is provided on the metallized layer 2 as shown in FIG. The semiconductor chip 5 is electrically connected by wire bonding using a thin gold wire 10, and the substrate of the semiconductor chip 5 is evenly lubricated through the terminal chip 6. Note that the wire bonding pad 11 formed on the semiconductor chip 5
are connected to the external lead frame 4 by wires 7, respectively. Furthermore, due to the high integration and high density of semiconductor devices,
It is designed to have poor heat resistance, so it is desirable to perform the treatment at as low a temperature as possible. Therefore, the adhesive sealing glasses 3 and 9 should be used at a sealing temperature as low as possible (approximately 400-480
℃).
前記導電性部材よりなる々−ミナルチップ６は第３図の
拡大断面図に示すようにコバール（鉄−ニッケル・コバ
ルト合金）、又は４２ア四イ（鉄−ニッケル４２％合金
）よりなる金属片１２の底部１３即ちメタライズ層２上
に対向する部分はたとえば金シリコンよりなる部材で形
成され、上部１４はたとえばアルミニウムーシリコン部
材より構成されており、上記ターミナルチップ６をメタ
ライズ層２上に接合する場合には約４００−４８０℃の
温度を加えて金−シリコン合金を溶融して接着が行なわ
れる。The terminal chip 6 made of the conductive material is a metal piece made of Kovar (iron-nickel cobalt alloy) or 42A4I (iron-nickel 42% alloy) as shown in the enlarged cross-sectional view of FIG. The bottom part 13 of 12, that is, the part facing the metallized layer 2, is formed of a member made of, for example, gold silicon, and the upper part 14 is made of, for example, an aluminum-silicon member, and the terminal chip 6 is bonded to the metallized layer 2. Bonding is sometimes accomplished by applying temperatures of about 400-480 DEG C. to melt the gold-silicon alloy.
しかしながらかかる多−ミナルチップは作業温度におい
て前記ガラス８が軟化し接着された外部リードフレーム
４の移動がおこる問題があった。However, such a multi-minal chip has a problem in that the glass 8 softens at working temperatures, causing movement of the external lead frame 4 to which it is bonded.
（ｄ−）発明の目的
本発明の目的はかかる問題点に低みなされたもので外部
リードフレームの移動を防止し、かつ半導体素子の劣化
を生じない構造を有する半導体装置の提供にある。(d-) Object of the Invention An object of the present invention is to provide a semiconductor device having a structure that prevents movement of an external lead frame and does not cause deterioration of semiconductor elements, in view of the above-mentioned problems.
（−）発明の構成
その目的を達成するため本発明はパッケージ基体に形成
されたメタライズ層に半導体チップと導１１Ｌ牲の金属
片とが固着され、かつ該金属片上にワイヤボンデングが
なきれてなり、該金属片は該メタウィズ層と対向する面
に鉛、又は鉛系合金層を有することを特徴とする。(-) Structure of the Invention In order to achieve the object, the present invention is characterized in that a semiconductor chip and a conductive metal piece are fixed to a metallized layer formed on a package base, and wire bonding is not performed on the metal piece. The metal piece is characterized in that it has a lead or lead-based alloy layer on the surface facing the metalwidth layer.
（０発明の実施例
以下本発明の実施例について図面を参照して船ｕｌ＋す
る。第４図は本発明の一実施例の半導体装置内に固着さ
れる導電性の金属片の拡大Ｍｉ面図であり前図と同等の
部分については同一符号を付している。(0 Examples of the Invention The following examples of the present invention will be described below with reference to the drawings. Figure 4 is an enlarged Mi side view of a conductive metal piece fixed in a semiconductor device according to an embodiment of the present invention. The same parts as in the previous figure are given the same reference numerals.
同図において彷・来と異なるｉｊは力市１性の金属片（
ターミナルチップ）２０のパッケージ基板に形成された
メタライズ層と対向する面に鉛、又は鉛合金系金属２１
を有する点である。In the same figure, ij, which is different from Aki and Lai, is a metal piece of Rikiichi 1 (
Lead or lead alloy metal 21 is placed on the surface facing the metallized layer formed on the package substrate of terminal chip) 20.
It is a point with .
即ち鉛、又は鉛合金系金属、たとえば鉛−錫一銀の所定
比に混合された合金、或は鉛−インジウムの所定比より
なる合金で形成されておりＱ）かるＩＦ＃ ＋ｓ′？の
々−ミナルチツプ２０を用いて約３２０℃以下σ）温度
でターミナルチップ２０をメタライズ＠２（第１図）ｌ
に接着出来る構造にしたことにある。That is, it is made of lead or a lead alloy metal, such as an alloy of lead and tin-silver mixed in a predetermined ratio, or an alloy of lead and indium in a predetermined ratio.Q) IF# +s'? Metallize the terminal chip 20 at a temperature of approximately 320°C or less using the terminal chip 20 @2 (Fig. 1)
The reason is that it has a structure that can be adhered to.
かかる構造によればパッケージ基体上面に接着された外
部リードフレームの移動が防止され、かつ低い封着温度
のガラスを使用することにより半導体素子の特性劣化の
危険性を防止することが可能となる。With this structure, movement of the external lead frame bonded to the top surface of the package base is prevented, and by using glass with a low sealing temperature, it is possible to prevent the risk of deterioration of the characteristics of the semiconductor element.
特性の劣化を防止し、かつ外部リードフレームの移動を
防止することが可能となり、製品の品質向上に効果があ
る。It is possible to prevent deterioration of characteristics and movement of the external lead frame, which is effective in improving product quality.
第１図は、従来装置の要Ｐｉｌｌｌ断面図、第２図は同
じくパッケージ基体の平面図、第３図は同じく導電性の
金属片の拡大断面図、第４図は本発明の一実施例の半導
体装置内に固着される導電性の金属片の拡大断面図であ
る。
同図において１はパッケージ基体、２はメタライズ層、
５は半導体チップ、ＩＯはワイヤ、２０は導電性の金属
片、２１は談金属片の対向な面の鉛、又は鉛合金系金４
を示す。
第１図
第２［ＩＷFIG. 1 is a cross-sectional view of the main pillar of the conventional device, FIG. 2 is a plan view of the package base, FIG. 3 is an enlarged cross-sectional view of the conductive metal piece, and FIG. 4 is a cross-sectional view of an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of a conductive metal piece fixed within a semiconductor device. In the figure, 1 is the package base, 2 is the metallized layer,
5 is a semiconductor chip, IO is a wire, 20 is a conductive metal piece, 21 is lead or lead alloy gold on the opposite side of the metal piece 4
shows. Figure 1 Figure 2 [IW
Claims (1)
プと導′ｌｌｊ、牲の金属片とが固着され、かつ該金民
片上にワイヤボンデングがなされてなり、該金属ハは該
メタライズ層と対向する面に、船又は鉛系合金−を有す
ることを特徴とする半導体装１行。A semiconductor chip and a conductive metal piece are fixed to a metallized layer formed on a package base, and wire bonding is performed on the metal piece, and the metal piece is attached to a surface facing the metallized layer. 1 row of semiconductor devices characterized by having a ship or a lead-based alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58134031A JPS6025257A (en) | 1983-07-21 | 1983-07-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58134031A JPS6025257A (en) | 1983-07-21 | 1983-07-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6025257A true JPS6025257A (en) | 1985-02-08 |
Family
ID=15118754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58134031A Pending JPS6025257A (en) | 1983-07-21 | 1983-07-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6025257A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58429B2 (en) * | 1974-08-07 | 1983-01-06 | ヒサミツセイヤク カブシキガイシヤ | Synquina 2-oxo-1,2,3,4-tetrahydropyride (2,3-D) Pyrimidine |
-
1983
- 1983-07-21 JP JP58134031A patent/JPS6025257A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58429B2 (en) * | 1974-08-07 | 1983-01-06 | ヒサミツセイヤク カブシキガイシヤ | Synquina 2-oxo-1,2,3,4-tetrahydropyride (2,3-D) Pyrimidine |
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