JPS58107679A - Field effect transistor - Google Patents

Abstract

PURPOSE:To achieve a high withstand voltage and a high gain without yielding strain in the interface between an operating layer and a buffer layer, by using a super lattice structure comprising a semiconductor material, which is the same as that of the operating layer and a semiconductor material whose band gap is larger than that of the former material, for the buffer layer. CONSTITUTION:A buffer layer 14, comprising an AlxGa1-xAs film 12 and a GaAs film 13, is provided. In this way, the leakage of carriers 8 can be prevented by the interface between the operating layer 3 and the super lattice layer 14 and a barrier formed in the buffer layer 14. The height of the barrier is changed by the number of the lattice of the buffer layer 14 and the film thickness of the GaAs film 13 and the AlxGa1-xAs film. Furtheremore, by using the buffer layer 14 in the super lattice structure, strain due to junction between different kinds can be prevented, and the degradation in crystal property of the operating layer 3 and the formation of interface traps between the operating layer 3 and the buffer layer 14 are prevented. Therefore, the effect of the prevention of the leakage of the carriers 8 to the buffer 14 is directly reflected to the element characteristics, the high withstand voltage of the GaAs FET and the high gain can be achieved, and high frequency characteristics can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to improvements in field effect transistors (IKTs).

Figure 1 is a schematic cross-sectional view showing the structure of an example of a conventional FET.
gallium arsenide (A/Ga1-, As) buffer layer (where O<c<1), (3) is an n-type GaAs active layer formed thereon, (4) l (5) and (6
) are the source electrode, gate electrode and drain electrode formed on the surface of the n-type GaAa operating layer (3), respectively, and (7
) is a depletion layer generated in the active layer (3) when a negative voltage of K is applied to the gate electrode (6), and (8) is an active carrier (electron).

The high breakdown voltage (high output) and high gain of such FETs are achieved in the high electric field operating layer region, that is, under the gate electrode (5), most of which becomes the depletion layer (7) and the operating layer (3) becomes extremely High-resistance buffer 7 layers (2
), but conventionally, as shown in Figure 1, a high-resistance buffer layer (2) is used.
A method has been to select a material with a larger band gap than the active layer (3) and utilize the barrier formed by the energy difference. Figure 2 shows the GaAs shown in Figure 1.
This is a diagram showing the energy band structure of FET, where E is 7.
engineering lumi level, E.

indicates the conduction band and E indicates the charging band. Carrier (8) #1G
aAa operating layer (3) and A4. A barrier formed at the interface with the Ga, As, high-resistance buffer layer (2) prevents injection into the high-resistance buffer layer (2). However, in this conventional FET, the strain due to the heterojunction is As shown schematically in No. 31'Q, dislocation (9)
enters the active layer (3), deteriorates its crystallinity, and forms traps at the interface. Even if the leakage of carriers (8) can be prevented as described above, the high frequency In addition to deteriorating the characteristics, the reverse breakdown voltage is also prevented from increasing.

This invention was made in consideration of the above-mentioned points, and by using a new structure for the buffer layer structure, it is possible to achieve different characteristics.
It is an object of the present invention to provide an FIT that reduces distortion due to m-coupling and does not have the above-mentioned conventional drawbacks.

That is, the present invention is based on the new finding that strain caused by dissimilar junctions is reduced by using a superlattice of the same material as the active layer and a material with a larger band gap than the active layer as the buffer layer.

Figure 4 is a schematic sectional view showing the configuration of an embodiment of the present invention.
The jlIs diagram is a diagram showing the structure of the energy band,
Parts equivalent to the conventional example are indicated by the same symbols. On is A/llGa.
1-1IAa Seven buffer layers consisting of a superlattice of I[H and a GaAs film aS.

By adopting this structure, the KS
=? The leakage of Yalya (8) can be prevented by the barrier formed at the interface between the active layer (3) and the superlattice layer (Tuffa layer) and within the buffer layer (141). (Number of superlattices of 14, Ga 8 film (l
@ and A/xGal-1llAs film (can be changed depending on the film thickness of If4.Furthermore, by using a superlattice structure for the buffer layer 04, distortion due to dissimilar junctions as in the conventional example can be prevented, and the active layer (3)
It is possible to prevent the deterioration of the crystallinity of the buffer layer (+4) and the formation of fast traps at the interface between the buffer layer (+4).Therefore, the leakage of carriers (8) to the buffer layer (+4) can be prevented, and the nine effect is directly reflected on the device characteristics. By doing so, it is possible to achieve higher breakdown voltage and higher gain of GaAsFE'l', and also improve high frequency characteristics.
This invention is not limited to GaAa.

The structure of the FET0 wafer according to the present invention can be easily formed by using the molecular epitaxy method.

As explained above, in the FE'E' according to the present invention, the superlattice structure of the same semiconductor material as the active layer and a semiconductor material with a large band gap is used for the buffer layer, so that the active layer and the buffer layer are No distortion occurs at the interface, high breakdown voltage and high gain can be achieved, and high frequency characteristics can also be improved.

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view showing the configuration of an example of conventional li'ET, Figure 2 is a diagram showing the structure of its energy band, and Figure 3 is the same diagram. FIG. 4 is a schematic λ cross-sectional view showing the configuration of an embodiment of the present invention, and FIG. 5 is a diagram showing the energy band structure of this embodiment. In the figure, (1) is a semiconductor substrate, (3) is an active semiconductor layer, (4) is a source electrode, (5) is a genite electrode, (6)
i drain electrode, t+2! J is a GaAs film (the same semiconductor as the semiconductor layer of Il1), 0 is Al, a GaAs film (a semiconductor with a larger band gap than the active semiconductor layer),
04 is a high resistance buffer 7 semiconductor layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno (1 other person) Figure 4 Figure 5

Claims (2)

[Claims] (1) A conductor substrate, a high-resistance buffer conductor layer, and an active semiconductor layer are sequentially formed in contact with each other, and a source electrode, a gate electrode, and a drain electrode are provided on the surface of the active semiconductor layer, in which the active semiconductor layer is provided with a source electrode, a gate electrode, and a drain electrode. A field effect transistor characterized in that a superlattice of the same semiconductor as the layer and a semiconductor having a larger band gap than the operating semiconductor layer is used as the high-resistance Batza semiconductor layer. (2) Adding gallium e arsenide (GaA) to the active semiconductor layer,
In the high resistance buffer semiconductor layer, gallium φ (GaAs) and aluminum φ gallium arsenide (Mul!) are used. , Ga1-. A field effect transistor according to item 1 of the claimed scope of patent #'I, characterized in that a superlattice with a superlattice structure (O<X1)) is used.