JPH04352332A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a field-effect transistor whose logical amplitude is large by applicating a large forward voltage to a gate. CONSTITUTION:A field-effect transistor has a gate part 5 which consists of an I-type or P-type barrier layer 2 having an energy band gap larger than that of a p-type Ge channel layer 1, an n-type semiconductor layer 3 and a gate electrode 6 formed in ohmic contact with this layer 3, is provided on the layer 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to field effect transistors, and particularly to p-channel type heterostructure field effect transistors having Ge as an active layer or channel layer.

0002

[Prior Art] GaAs, a III-V compound semiconductor
The mobility of electrons in Si is 4 to 5 times higher than in Si, so various electronic devices such as n-channel field effect transistors (FETs) with GaAs as the active layer are used today as high-speed, high-frequency devices. It has been put into practical use.

In order to increase the speed and reduce the power consumption of an IC (integrated circuit), it is important to adopt a complementary circuit configuration, that is, a combination of p-channel and n-channel FETs.

However, at present, high-speed devices using holes as carriers have not been sufficiently developed and put into practical use. For example, the mobility of holes in GaAs is μh (250 μh at room temperature)
cm2/V・sec) is the electron mobility μe (8 at room temperature
600cm2/V・sec),
When a complementary circuit is created using GaAs as the active layer, there is a problem in that the characteristics of the entire circuit are restricted by the characteristics of the p-channel FET.

On the other hand, it has recently attracted attention that the hole mobility μh in Ge is as large as 1900 cm2/V·sec at room temperature, but the Schottky barrier of metal-Ge (approximately 0.3 e
V), and the barrier caused by the Ge pn junction (0.4 to 0.6
eV) are both relatively low, and only these
Even if T is configured, the logic amplitude cannot be obtained much.

On the other hand, as shown in FIG. 4, Ge
A heterostructure FE that uses the holes inside as a carrier for the FET
T has been proposed. This is an intrinsic (i-type) Al0.3 Ga0.7 As on an n-type GaAs substrate 21.
Semiconductor layer 22, p-type Ge layer 23, and intrinsic Al0.3G
It has a structure in which a semiconductor layer 24 made of a0.7 As is grown in sequence, and a gate electrode 25 made of Al or the like constituting the Schottky junction Js is deposited on this semiconductor layer 24. Reference numerals 26 and 27 indicate source and drain electrodes ohmically deposited on the p-type channel layer or active layer 23.

However, with this configuration, Al
The so-called (Doped Channel MISLik
Even in an n-channel GaAs junction FET (J-FET), the logic amplitude is lower than, for example, 1.4 eV, because the forward voltage cannot be made sufficiently large in an n-channel GaAs junction FET (J-FET). When constructing a complementary logic circuit with a GaAs J-FET, there is a concern that the advantage of the large logic amplitude of the J-FET cannot be fully utilized.

[0008]

SUMMARY OF THE INVENTION The present invention aims to increase the logic amplitude by increasing the forward voltage in a heterostructure field effect transistor having Ge as an active layer.

[Means for Solving the Problems] As shown in a schematic cross-sectional view of an example of the present invention in FIG. Intrinsic (
The structure includes an i-type or p-type barrier layer 2, an n-type semiconductor layer 3, and a junction type gate portion 5 consisting of a gate electrode 4 ohmically deposited thereon.

Reference numerals 6 and 7 indicate source electrodes and drain electrodes arranged in ohmic contact with the p-type Ge channel layer 1 on both sides of the gate portion 5, with the gate portion 5 in between.

That is, in the present invention, an n-i-p or n-p-p type junction is formed between an i-type or p-type barrier layer 2 and an n-type semiconductor layer 3 for a p-type Ge channel layer. Due to the so-called J-FET configuration having a gate part,
A heterostructure field effect transistor configuration is adopted in which Ge is used as an active layer.

[0011]

[Function] Figure 2 shows an FE in which the barrier layer 2 of the present invention is i-type.
2A shows a band model diagram of an example of a normally-on type FET, in particular, in this case, FIG. 2A shows a band model diagram of a thermal equilibrium state.

In FIG. 2A, the broken line band model diagram shows a comparison of the DMT structure in which the gate portion is a Schottky gate.

[0013] Now, if the voltage required to apply a forward bias to create a flat band state is φFB, then φFB = Eg - ΔEn - ΔEp - ΔEv (Eg is the band gap between the semiconductor layer 3 and the barrier layer 2). , ΔEn and ΔE
p is the donor level and acceptor level, and ΔEv is the discontinuity value of the valence band between the barrier layer 2 and the p-type Ge channel layer 1). Here, since ΔEn and ΔEp are negligibly small values, φFB≈Eg−ΔEv. When the barrier layer 2 and the semiconductor layer 3 are GaAs, Eg=
1.42eV, ΔEv=0.68eV, so φF
B≒0.72 eV.

[0014] In contrast, the DMT
In the case of the structure, if the barrier layer is made of AlGaAs as described above, Eg=1.2 eV and ΔEv=0.81 eV, so φFB is about 0.39 eV. From this, the FET of the present invention has a significantly improved flat band potential compared to DMT. Therefore, the maximum allowable forward voltage is improved.

FIG. 3A shows a band model of thermal equilibrium state when the barrier layer 2 is p-type; in this case, φF
B=Eg−ΔEn−ΔEp, and as mentioned above, Δ
Since En and ΔEp can be ignored, φFB≒Eg=1
．． It can show a high value of 42ev. Note that even if a forward voltage is actually applied to the gate electrode 4, this voltage has a modulation component that modulates the band of the p-Ge channel layer 1, so the actual flat band when passing through the barrier layer 2 is The potential becomes a voltage larger than φFB.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A FET according to the present invention will be explained with reference to FIG. In this case, a p-type Ge channel layer 1 is successively formed on a substrate 10 made of, for example, intrinsic (i-type) GaAs, by, for example, MOCVD (metal-organic chemical vapor deposition) or MBE (molecular beam epitaxy), In contrast, intrinsic energy has a sufficiently large energy bandgap, has good matching with Ge, and forms a barrier to holes in thermal equilibrium (
A barrier layer 2 made of (i-type) GaAs and an n-type GaAs
An n-i-p junction type gate portion 5 is formed by epitaxially growing a semiconductor layer 3 and a gate electrode 4 ohmically deposited on this semiconductor layer 3.

The gate electrode 4 may be composed of, for example, an Au-Ge/Ni alloy layer that can be ohmically adhered to the GaAs semiconductor layer 3.

Further, the n-type semiconductor layer 3 and the barrier layer 2 may be removed from at least part of both sides of the gate portion 5, or the gate portion 5 may be formed only on the channel layer 1. The p-type Ge channel layer 1 on both sides is exposed to the outside, and a source electrode 6 and a drain electrode 7 are ohmically deposited thereon, respectively.

[0019] Here, GaAs and Ge have good crystal compatibility.

FIG. 2 shows a band model diagram of an FET with this configuration. FIG. 2A shows a thermal equilibrium state, and FIG. 2B shows a state where the channel is depleted by applying a reverse bias.

According to this configuration, as already explained with reference to FIG. 2, the voltage φFB required to achieve the flat band state can be set to about 0.72 eV, so that the voltage φFB can be applied to the gate in the forward direction. The voltage, that is, the logic amplitude can be sufficiently increased.

In the above example, the barrier layer 2 has an i-type structure, but the barrier layer 2 can also be of a p-type. The band model diagram in this case is as shown in FIG. 3, similarly, FIG. 3A shows a thermal equilibrium state, and FIG. 3B shows a reverse bias applied state.

[0023] When forming an n-p junction in GaAs in the gate portion to form an n-p-p structure, a large forward voltage is applied as explained in the ``effect'' section above. Therefore, the logic amplitude can be made larger.

[0024] In this way, F with a large logic amplitude
By configuring an ET, a circuit with a large noise margin can be configured, and by configuring a complementary circuit with good characteristics, power consumption can be reduced.

Furthermore, in the examples shown in FIGS. 2 and 3, a band model of a normally-on type FET is shown. For example, the doping amount of the barrier layer 2 is reduced, and its thickness By reducing the thickness of the Ge channel layer, a normally-off type FET can be constructed by forming a depletion state in the channel layer as shown in FIG. 2B in a thermal equilibrium state.

[0026] Furthermore, the FET according to the present invention may be made of a common GaA
When forming an n-channel FET on an s-substrate 10, for example, a p-type G is formed on a part of the GaAs substrate 10.
An e-channel layer is formed, on which the above-described FET according to the present invention is constructed, and in other parts, for example, an n-channel type FET is constructed using a GaAs channel layer to construct various IC structures, such as a complementary structure. be able to.

[0027]

Effects of the Invention According to the present invention described above, by adopting a heterostructure field effect transistor structure in which p-Ge is used as an active layer, the mobility for holes is increased, so that a high-speed hole (hole) device can be realized. In addition, although it is based on the Ge active layer, by adopting a pn junction structure as the gate part, a large forward voltage VF can be applied, so a large logic amplitude can be obtained. This allows a circuit with a large noise margin to be constructed.

In addition, it is possible to improve characteristics such as logic amplitude and high speed to the same extent as n-channel FETs, and it is possible to obtain, for example, a p-channel type heterostructure field effect transistor that is advantageous for complementary construction, which is of great practical importance. have a profit.

[Brief explanation of the drawing]

FIG. 1 is a schematic enlarged cross-sectional view of an example of a field effect transistor according to the present invention.

FIG. 2 is the band model.

FIG. 3 is a band model diagram of another example.

FIG. 4 is a schematic enlarged cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

10 Base 1 p-type Ge channel layer 2 Barrier layer 3 N-type semiconductor layer 4 Gate electrode 5 Gate part

Claims (1)

[Claims] 1. An intrinsic or p-type barrier layer formed of a compound semiconductor epitaxially grown layer that matches the channel layer and has a larger energy bandgap than that of the channel layer, on the p-type Ge channel layer; 1. A field effect transistor comprising: n-type semiconductor layers stacked one after another, and a junction-type gate portion having a gate electrode ohmically deposited on the n-type semiconductor layer.