JP3042019B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a heterostructure field effect transistor having a p-channel Ge as an active layer, that is, a channel layer.

[0002]

2. Description of the Related Art The mobility of electrons in III-V compound semiconductors in GaAs is 4 to 5 times higher than that in Si.
Various electronic devices including an n-channel field-effect transistor (FET) having an active layer of aAs have been put to practical use today as high-speed and high-frequency devices.

In order to reduce the power consumption of an IC (integrated circuit) in addition to the increase in speed, it is important to adopt a complementary, ie, a circuit configuration using a combination of p-channel and n-channel FETs.

However, at present, high-speed devices using holes (holes) as carriers are not sufficiently developed and put into practical use. For example, the mobility μh of holes in GaAs (25 at room temperature)
0 cm ² / V · sec) is the electron mobility μe (86 at room temperature).
00 cm ² / V · sec)
When s is used as an active layer to create a complementary circuit, p
There is a problem that the characteristics of the entire circuit are restricted by the characteristics of the channel FET.

On the other hand, it has recently been noted that the hole mobility μh in Ge is as large as 1900 cm ² / V · sec at room temperature, but the metal-Ge Schottky barrier (about 0.3 e
V) and the barrier due to the pn junction of Ge (0.4 to 0.6).
eV) are relatively low, and FE alone
Even if T is configured, a large logical amplitude cannot be obtained.

On the other hand, as shown in FIG.
Ge as disclosed in Kaihei 2-181935
Structure FE using holes in FET as carrier of FET
T has been proposed. This is an n-type GaAs substrate
21 on the intrinsic (i-type) Al _0.3Ga_0.7As semiconductor layer
22 and p-type Ge layer 23 and intrinsic Al_0.3Ga_0.7As
And a semiconductor layer 24 formed in this order.
Constituting the Schottky junction Js on the semiconductor layer 24 of FIG.
A configuration in which a gate electrode 25 such as 1 is attached is adopted. 2
6 and 27 are on the p-type channel layer, that is, the active layer 23.
Ohmicly deposited source and drain electrodes
Show.

However, Al having such a structure has
Even in a so-called DMT (Doped Channel MISLike FET) having a metal / insulating layer / semiconductor structure having an insulating layer of GaAs, the forward voltage cannot be sufficiently increased. J-FET) logic amplitude 1.4e
Lower than V, J-F by this n-channel GaAs
When configuring a complementary logic circuit with ET,
Again, there is a concern that the superiority of the large logic amplitude of the J-FET cannot be fully utilized.

[0008]

SUMMARY OF THE INVENTION The present invention aims at increasing the logic amplitude by increasing the forward voltage of a heterostructure field effect transistor using Ge as an active layer.

According to the present invention, as shown in a schematic sectional view of one example in FIG. 1, a p-type Ge channel layer (active layer) 1 An intrinsic (i-type) or p-type barrier layer 2 comprising an epitaxially grown GaAs compound semiconductor layer having an energy band gap sufficiently larger than that of the channel layer 1, and an n-type semiconductor layer 3
And a junction type gate portion 5 composed of a gate electrode 4 that is ohmicly adhered thereon.

Reference numerals 6 and 7 denote a source electrode and a drain electrode by ohmic contact disposed on both sides of the gate portion 5 with respect to the p-type Ge channel layer 1, respectively.

That is, in the present invention, the nip or npp junction type of the i-type or p-type barrier layer 2 and the n-type semiconductor layer 3 with respect to the p-type Ge channel layer. With a so-called J-FET configuration having a gate,
A hetero-structure field effect transistor having Ge as an active layer is employed.

[0011]

FIG. 2 shows an FE in which the barrier layer 2 of the present invention is i-type.
FIG. 2A shows a band model diagram of an example of a normally-on type FET of T. In this case, FIG. 2A shows a band model diagram in a thermal equilibrium state.

In FIG. 2A, a dashed band model diagram shows a comparison between the case of the DMT structure in which the gate portion is a Schottky gate.

Assuming that a voltage required for applying a forward bias to make a flat band state is φ _FB , this φ _FB is φ φ
_FB = Eg−ΔEn−ΔEp−ΔEv (Eg is the semiconductor layer 3
And the band gap of the barrier layer 2, ΔEn and ΔEp are the donor level and the acceptor level, and ΔEv is the discontinuous value of the valence band between the barrier layer 2 and the p-type Ge channel layer 1. Here, since the ΔEn and ΔEp is a small value enough to be ignored, the φ _FB ≒ Eg-ΔEv. When the barrier layer 2 and the semiconductor layer 3 are GaAs, Eg = 1.42
Since eV and ΔEv = 0.68 eV, φ _FB ≒ 0.7
2 eV.

In contrast, the DMT shown by the broken line in FIG.
In the case of the structure, when the barrier layer is made of AlGaAs as described above, since Eg = 1.2 eV and ΔEv = 0.81 eV, φ _FB is about 0.39 eV. For this reason, the flat band potential of the FET of the present invention is remarkably improved as compared with DMT. Therefore, the maximum allowable forward voltage is improved.

FIG. 3A shows a band model in a thermal equilibrium state when the barrier layer 2 is p-type. In this case, φ _FB
= Eg−ΔEn−ΔEp, and as described above, ΔE
Since n and ΔEp can be ignored, φ _FB ≒ Eg = 1.4
A high value of 2 ev can be shown. Even if a forward voltage is actually applied to the gate electrode 4, this voltage is p
Since a modulation component for modulating the band of the channel layer 1 of -Ge is generated, the actual flat band potential through the barrier layer 2 is a voltage larger than φ _FB .

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An FET according to the present invention will be described with reference to FIG. In this case, for example, a p-type Ge channel layer 1 is continuously formed on a substrate 10 made of, for example, intrinsic (i-type) GaAs by, for example, MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy). On the other hand, a barrier layer 2 made of intrinsic (i-type) GaAs having a sufficiently large energy band gap, good matching with Ge, and a barrier to holes in a thermal equilibrium state, and n-type GaAs
The s-type semiconductor layer 3 is epitaxially grown, and a gate electrode 4 is ohmically deposited on the semiconductor layer 3 to form a nip junction type gate portion 5.

The gate electrode 4 can be composed of, for example, an Au—Ge / Ni alloy layer that can be ohmically adhered to the GaAs semiconductor layer 3.

The n-type semiconductor layer 3 and the barrier layer 2 are removed at least on both sides of the gate portion 5 or the gate portion 5 is formed only on the channel layer 1 so that the gate portion 5 is formed. The p-type Ge channel layer 1 on both sides is exposed to the outside, and the source electrode 6 and the drain electrode 7 are respectively ohmicly deposited thereon.

Here, GaAs and Ge have good crystallinity.

FIG. 2 shows an FET band model diagram of this configuration. FIG. 2A shows a thermal equilibrium state, and FIG. 2B shows a state in which the channel is depleted by applying a reverse bias.

According to this configuration, as described with reference to FIG. 2, the voltage φ _FB required for bringing into the flat band state can be reduced to about 0.72 eV.
The voltage which can be applied to the gate in the forward direction, that is, the logic amplitude can be sufficiently increased.

In the above-described example, the barrier layer 2 has an i-type configuration. However, the barrier layer 2 may be a p-type. The band model diagram in this case is as shown in FIG. 3. Similarly, FIG. 3A shows a thermal equilibrium state, and FIG. 3B shows a reverse bias applied state.

In the case where the n-p-p structure is formed by forming the n-p junction in the GaAs in the gate portion, a large forward voltage is applied as described in the section of "action". As a result, the logic amplitude can be made larger.

Then, as described above, F having a large logic amplitude
By configuring the ET, a circuit having a large noise margin can be configured, and by configuring a complementary circuit having good characteristics, power consumption can be reduced.

2 and 3 show the band model of a normally-on type FET. For example, the doping amount of the barrier layer 2 is reduced, and the thickness and p-type of the barrier layer 2 are reduced. By reducing the thickness of the Ge channel layer, a normally-off type FET can be formed by forming a depleted state as shown in FIG. 2B in the channel layer in a thermal equilibrium state.

Further, the FET according to the present invention can be used in common GaAs.
When formed together with an n-channel FET on the s substrate 10, for example, the p-type G
An e-channel layer is formed thereon, and the above-described FET according to the present invention is formed thereon, and other IC structures such as an n-channel type FET formed of a GaAs channel layer are formed on other parts to be complementary. be able to.

[0027]

According to the present invention described above, the adoption of a heterostructure field effect transistor structure using p-Ge as an active layer enhances the mobility for holes, thereby realizing a high-speed hole (hole) device. In addition to being able to obtain a large forward voltage V _F by adopting a pn junction structure as a gate portion thereof despite the Ge active layer, a large logic amplitude can be obtained. Thus, a circuit having a large noise margin can be configured.

In addition, it is possible to improve the characteristics such as the logic amplitude and the high-speed property of the same level as the n-channel FET, and to obtain a p-channel type heterostructure field effect transistor which is advantageous for the complementary operation, for example. Have a profit.

[Brief description of the drawings]

FIG. 1 is a schematic enlarged cross-sectional view of an example of a field-effect transistor according to the present invention.

FIG. 2 is a band model thereof.

FIG. 3 is a band model diagram of another example.

FIG. 4 is a schematic enlarged cross-sectional view of a conventional field-effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 1 p-type Ge channel layer 2 barrier layer 3 n-type semiconductor layer 4 gate electrode 5 gate part

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 29/80-29/812 H01L 29/775-29/778

Claims (1)

(57) [Claims] 1. An intrinsic or p-type barrier layer comprising a GaAs compound semiconductor epitaxial growth layer, which is aligned with the channel layer and has an energy band gap larger than that of the channel layer, on the p-type Ge channel layer; A field effect transistor comprising: a semiconductor layer; and a junction type gate portion in which a gate electrode is ohmicly provided on the n-type semiconductor layer.