JPS58102532A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58102532A
JPS58102532A JP20098081A JP20098081A JPS58102532A JP S58102532 A JPS58102532 A JP S58102532A JP 20098081 A JP20098081 A JP 20098081A JP 20098081 A JP20098081 A JP 20098081A JP S58102532 A JPS58102532 A JP S58102532A
Authority
JP
Japan
Prior art keywords
copper
pellet
thermal expansion
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20098081A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0376578B2 (en:Method
Inventor
Keizo Tani
谷　敬造
Kenichi Muramoto
村本　顕一
Yutaka Tomizawa
富澤　豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP20098081A priority Critical patent/JPS58102532A/ja
Publication of JPS58102532A publication Critical patent/JPS58102532A/ja
Publication of JPH0376578B2 publication Critical patent/JPH0376578B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP20098081A 1981-12-15 1981-12-15 半導体装置 Granted JPS58102532A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20098081A JPS58102532A (ja) 1981-12-15 1981-12-15 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20098081A JPS58102532A (ja) 1981-12-15 1981-12-15 半導体装置

Publications (2)

Publication Number Publication Date
JPS58102532A true JPS58102532A (ja) 1983-06-18
JPH0376578B2 JPH0376578B2 (en:Method) 1991-12-05

Family

ID=16433508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20098081A Granted JPS58102532A (ja) 1981-12-15 1981-12-15 半導体装置

Country Status (1)

Country Link
JP (1) JPS58102532A (en:Method)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089935A (ja) * 1983-10-21 1985-05-20 Hitachi Ltd 半導体装置
US6605868B2 (en) * 1998-12-10 2003-08-12 Kabushiki Kaisha Toshiba Insulating substrate including multilevel insulative ceramic layers joined with an intermediate layer
US7750310B2 (en) 2005-08-16 2010-07-06 Hitachi, Ltd. Semiconductor radioactive ray detector, radioactive ray detection module, and nuclear medicine diagnosis apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917381A (en:Method) * 1972-04-20 1974-02-15
JPS55128837A (en) * 1979-03-28 1980-10-06 Nec Corp Base for mounting semiconductor chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917381A (en:Method) * 1972-04-20 1974-02-15
JPS55128837A (en) * 1979-03-28 1980-10-06 Nec Corp Base for mounting semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089935A (ja) * 1983-10-21 1985-05-20 Hitachi Ltd 半導体装置
US6605868B2 (en) * 1998-12-10 2003-08-12 Kabushiki Kaisha Toshiba Insulating substrate including multilevel insulative ceramic layers joined with an intermediate layer
US7750310B2 (en) 2005-08-16 2010-07-06 Hitachi, Ltd. Semiconductor radioactive ray detector, radioactive ray detection module, and nuclear medicine diagnosis apparatus

Also Published As

Publication number Publication date
JPH0376578B2 (en:Method) 1991-12-05

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