JPS5791551A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5791551A
JPS5791551A JP16739880A JP16739880A JPS5791551A JP S5791551 A JPS5791551 A JP S5791551A JP 16739880 A JP16739880 A JP 16739880A JP 16739880 A JP16739880 A JP 16739880A JP S5791551 A JPS5791551 A JP S5791551A
Authority
JP
Japan
Prior art keywords
film
conductive
type
terminals
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16739880A
Other languages
Japanese (ja)
Inventor
Kunimitsu Fujiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16739880A priority Critical patent/JPS5791551A/en
Publication of JPS5791551A publication Critical patent/JPS5791551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a semiconductor element area by exposing part of the second conductive type semiconductor layer formed on the first conductive type semiconductor layer to form the second conductive type channel connecting the second conductive type semiconductor layer. CONSTITUTION:An N type epitaxially grown layer 2 is formed on a P type silicon substrate 1, a P type diffusion 3 for isolating elements is formed, and P<+> type diffusions 41-44 becoming terminals are formed on the grown layer. Thereafter, an oxidized film 5 is formed on the overall surface, a recess groove 6 of a depth w for connecting the terminal groups 41-44 are formed, and an inversion preventing region 83 formed of an N<+> is formed by ion implantation. Then, a thin insulating film 9 having a thickness t is formed, contacting holes 111-114 connected respectively to the terminals 41-44 are opened at the film 5, a conductive film 10 is vapor-deposited on the entire surface, and a gate terminal 125 connected to the resistor terminals 121-124 and a conductive film 10 is provided.
JP16739880A 1980-11-29 1980-11-29 Semiconductor device Pending JPS5791551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16739880A JPS5791551A (en) 1980-11-29 1980-11-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16739880A JPS5791551A (en) 1980-11-29 1980-11-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5791551A true JPS5791551A (en) 1982-06-07

Family

ID=15848957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16739880A Pending JPS5791551A (en) 1980-11-29 1980-11-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5791551A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017504A (en) * 1986-12-01 1991-05-21 Mitsubishi Denki Kabushiki Kaisha Vertical type MOS transistor and method of formation thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017504A (en) * 1986-12-01 1991-05-21 Mitsubishi Denki Kabushiki Kaisha Vertical type MOS transistor and method of formation thereof

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