JPS5790936A - Impurity diffusing method - Google Patents

Impurity diffusing method

Info

Publication number
JPS5790936A
JPS5790936A JP16889280A JP16889280A JPS5790936A JP S5790936 A JPS5790936 A JP S5790936A JP 16889280 A JP16889280 A JP 16889280A JP 16889280 A JP16889280 A JP 16889280A JP S5790936 A JPS5790936 A JP S5790936A
Authority
JP
Japan
Prior art keywords
wafer
type
source
diffusing
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16889280A
Other languages
Japanese (ja)
Inventor
Shizutaka Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16889280A priority Critical patent/JPS5790936A/en
Publication of JPS5790936A publication Critical patent/JPS5790936A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain normal P-N junction securely when a semiconductor wafer is held between a P type, impurity film state, diffusing source and an N type, impurity film state, diffusing source and the diffusion treatment is performed, by performing alternate lamination so that P type film is larger than the wafer and the N type film is smaller than the wafer. CONSTITUTION:A quartz rod 2 is placed on a quartz boat 1. The P type, impurity film state, diffusing source 3a whose configuration is larger than the semiconductor wafer 4 which is to be diffused is placed on the rod 2. The wafer 4 is placed thereon, and is held by the N type, impurity film state, diffusing source 5 whose configuration is smaller than the wafer 4. In this case, the diameter of the P type diffusing source 3a is larger than that of the wafer 4 by about 2mm., and the diameter of the N type diffusing source 5a is smaller by about 3mm.. Then, they are alternately layered and placed within the even heat band in the diffusing furnace, and desired diffusion is performed. In this method, even though the diffusion source 3a contracts, it does not become smaller than the wafer 4, and excessive impurities from the impurity source 5a do not reach the wafer 4.
JP16889280A 1980-11-27 1980-11-27 Impurity diffusing method Pending JPS5790936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16889280A JPS5790936A (en) 1980-11-27 1980-11-27 Impurity diffusing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16889280A JPS5790936A (en) 1980-11-27 1980-11-27 Impurity diffusing method

Publications (1)

Publication Number Publication Date
JPS5790936A true JPS5790936A (en) 1982-06-05

Family

ID=15876497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16889280A Pending JPS5790936A (en) 1980-11-27 1980-11-27 Impurity diffusing method

Country Status (1)

Country Link
JP (1) JPS5790936A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5094976A (en) * 1988-07-14 1992-03-10 Kabushiki Kaisha Toshiba Dopant film and methods of diffusing impurity into and manufacturing a semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5094976A (en) * 1988-07-14 1992-03-10 Kabushiki Kaisha Toshiba Dopant film and methods of diffusing impurity into and manufacturing a semiconductor wafer

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